IP Library › Granted Patent US 12,034,027
Granted Patent B2
US 12,034,027 · App. 17/408,257 · Granted Jul 9, 2024

Semiconductor device contact pad and method of contact pad fabrication

Inventor: Hui Zang (San Jose, CA)
Assignee: OMNIVISION TECHNOLOGIES, INC.
H01L27/14632H01L27/14636H01L27/14645H01L27/14687H01L27/14698
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Quick Facts
Patent No.
US 12,034,027
App. No.
17/408,257
Granted
Jul 9, 2024
Kind
B2
Abstract

A method for forming a contact pad of a semiconductor device is disclosed. The method includes providing a semiconductor substrate including a first side and a second side. The semiconductor device includes a shallow trench isolation structure, disposed between the first side and the second side, and an intermetal dielectric stack coupled to the second side. The intermetal dielectric stack includes a first metal interconnect. The method further includes etching a first trench into the semiconductor substrate, depositing a dielectric material into the first trench to form a dielectric spacer extending along side walls of the first trench, etching a second trench aligned with the first trench, and depositing a metal material into the second trench to form the contact pad that contacts the first metal interconnect.

Claims (43)

1. A method for forming a contact pad of a semiconductor device, the method comprising:

etching a first trench into a semiconductor substrate during a first etching step, wherein the semiconductor substrate includes a first side and a second side opposite the first side, wherein the semiconductor device includes a shallow trench isolation (STI) structure disposed between the first side and the second side of the semiconductor substrate, wherein the semiconductor device further includes an intermetal dielectric stack coupled to the second side of the semiconductor substrate, wherein the intermetal dielectric stack includes a first metal interconnect, and wherein the first trench extends from the first side of the semiconductor substrate to the STI structure;

depositing a dielectric material into the first trench during a dielectric deposition step to form a dielectric spacer extending along side walls of the first trench;

etching a second trench aligned with the first trench during a second etching step based, at least in part, on the dielectric spacer, wherein the second trench extends through the STI structure to the first metal interconnect;

depositing a metal material into the second trench during a metal deposition step to form the contact pad, wherein the contact pad contacts the first metal interconnect; and

depositing an etch stop layer before the dielectric material is deposited such that the etch stop layer is disposed between the dielectric material and the first side of the semiconductor substrate, wherein the etch stop layer has etching selectivity relative to subsequently deposited materials such that the etch stop layer has a lower etch rate relative to etch rates of the dielectric material and the metal material.

2. The method of claim 1 , wherein a first width of the first trench is greater than a second width of the second trench, and wherein the second width is defined based on a difference between the first width and a thickness of the dielectric spacer.

3. The method of claim 2 , further comprising:

overlaying the etch stop layer with a pattern using a photomask for at least forming the first trench.

4. The method of claim 3 , further comprising:

anisotropically etching the dielectric material during an anisotropic etch step after the dielectric deposition step, wherein during the dielectric deposition step the dielectric material conformally coats the etch stop layer, the side walls of the first trench, and an exposed region of the STI structure, and wherein the anisotropic etch step removes the dielectric material coating the etch stop layer and the exposed region of the STI structure to form the dielectric spacer.

5. The method of claim 4 , wherein the metal material at least partially fills the first trench and the second trench such that the metal material is laterally surrounded by the dielectric spacer, and wherein the metal material further extends over the etch stop layer such that the etch stop layer is disposed between the metal material and the first side of the semiconductor substrate.

6. The method of claim 5 , further comprising:

etching the metal material during a metal etch step to remove excess portions of the metal material contacting the etch stop layer and further remove a portion of the metal material laterally surrounded by the dielectric spacer in the first trench to form the contact pad; and

removing the etch stop layer.

7. The method of claim 3 , wherein the second etching step, which forms the second trench with the second width less than the first width of the first trench, is performed using the photomask and without any additional photomasks.

8. The method of claim 1 , wherein the metal material conformally contacts the dielectric spacer to form a third trench disposed between metal side walls of the metal material.

9. The method of claim 8 , further comprising:

depositing a second etch stop layer into the third trench such that the second etch stop layer is disposed between the metal side walls of the metal material, wherein the metal material includes a first segment disposed between the second etch stop layer and the first metal interconnect, and wherein other segments of the metal material not disposed between the second etch stop layer and the first metal interconnect form the metal side walls;

etching the other segments of the metal material to remove the metal side walls and form the contact pad, wherein the contact pad is disposed between the second etch stop layer and the first metal interconnect; and

removing the second etch stop layer.

10. The method of claim 9 , wherein a first height of the contact pad is less than a first depth of the second trench, and wherein the first depth of the second trench corresponds to a distance from the first metal interconnect to a first interface where the dielectric spacer contacts the STI structure.

11. The method of claim 1 , wherein the semiconductor substrate corresponds a semiconductor wafer including a plurality of dies, each die included in the plurality of dies corresponding to an instance of the semiconductor device, and wherein each of the plurality of dies are separated from one another by scribe lines indicative of where to dice the semiconductor wafer.

12. The method of claim 11 , wherein at least one die, included in the plurality of dies, includes a second contact pad disposed within a backside scribe line region of the at least one die, wherein the second contact pad is disposed proximate to at least one of the scribe lines, and wherein the second contact pad disposed within the backside scribe line region is formed simultaneously with the contact pad during the first etching step, the dielectric deposition step, the second etching step, and the metal deposition step.

13. The method of claim 11 , wherein the semiconductor device is an image sensor.

14. The method of claim 1 , wherein the metal material only partially fills the first trench.

15. The method of claim 1 , wherein the etch stop layer includes a high-k dielectric material having a dielectric constant greater than silicon dioxide.

16. The method of claim 1 , wherein the dielectric material includes silicon nitride.

17. The method of claim 1 , wherein the dielectric material is different than the etch stop layer.

18. A method for forming a contact pad of a semiconductor device, the method comprising:

etching a first trench into a semiconductor substrate during a first etching step, wherein the semiconductor substrate includes a first side and a second side opposite the first side, wherein the semiconductor device includes a shallow trench isolation (STI) structure disposed between the first side and the second side of the semiconductor substrate, wherein the semiconductor device further includes an intermetal dielectric stack coupled to the second side of the semiconductor substrate, wherein the intermetal dielectric stack includes a first metal interconnect, and wherein the first trench extends from the first side of the semiconductor substrate into the STI structure;

depositing a dielectric material into the first trench during a dielectric deposition step to form a dielectric spacer extending along side walls of the first trench, wherein the side walls of the first trench extend, at least in part, into the STI structure such that the STI structure is disposed between the semiconductor substrate and the dielectric material;

etching a second trench aligned with the first trench during a second etching step based, at least in part, on the dielectric spacer, wherein the second trench extends through the STI structure to the first metal interconnect; and

depositing a metal material into the second trench during a metal deposition step to form the contact pad, wherein the contact pad contacts the first metal interconnect,

wherein the first trench is etched through a dielectric layer during the first etching step, the dielectric layer including a metal grid embedded therein, wherein the dielectric spacer extends continuously through the dielectric layer until reaching the STI structure before and after the metal deposition step.

19. A method for forming a contact pad of a semiconductor device, the method comprising:

etching a first trench into a semiconductor substrate during a first etching step, wherein the semiconductor substrate includes a first side and a second side opposite the first side, wherein the semiconductor device includes a shallow trench isolation (STI) structure disposed between the first side and the second side of the semiconductor substrate, wherein the semiconductor device further includes an intermetal dielectric stack coupled to the second side of the semiconductor substrate, wherein the intermetal dielectric stack includes a first metal interconnect, and wherein the first trench extends from the first side of the semiconductor substrate to the STI structure;

depositing a dielectric material into the first trench during a dielectric deposition step to form a dielectric spacer extending along side walls of the first trench;

etching a second trench aligned with the first trench during a second etching step based, at least in part, on the dielectric spacer, wherein the second trench extends through the STI structure to the first metal interconnect;

depositing a metal material into the second trench during a metal deposition step to form the contact pad, wherein the contact pad contacts the first metal interconnect, wherein the metal material conformally contacts the dielectric spacer to form a third trench disposed between metal side walls of the metal material;

depositing a second etch stop layer into the third trench such that the second etch stop layer is disposed between the metal side walls of the metal material, wherein the metal material includes a first segment disposed between the second etch stop layer and the first metal interconnect, and wherein other segments of the metal material not disposed between the second etch stop layer and the first metal interconnect form the metal side walls;

etching the other segments of the metal material to remove the metal side walls and form the contact pad, wherein the contact pad is disposed between the second etch stop layer and the first metal interconnect; and

removing the second etch stop layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2021
From: ZANG, HUI
To: OMNIVISION TECHNOLOGIES, INC.
Reel/Frame 057245/0920 →
Continuity (1)
Related Publication 20230053960A1 · Feb 23, 2023
Cited By (1)
US 12,532,562