IP Library › Granted Patent US 12,034,964
Granted Patent B2
US 12,034,964 · App. 17/401,438 · Granted Jul 9, 2024

Selective application of decoder side refining tools

Inventors: Hongbin Liu (Beijing, CN); Li Zhang (San Diego, CA); Kai Zhang (San Diego, CA); Jizheng Xu (San Diego, CA); Yue Wang (Beijing, CN)
Assignees: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD; BYTEDANCE INC.
H04N19/52H04N19/132H04N19/137H04N19/139H04N19/159H04N19/176H04N19/184H04N19/186H04N19/46H04N19/513H04N19/577
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Quick Facts
Patent No.
US 12,034,964
App. No.
17/401,438
Granted
Jul 9, 2024
Kind
B2
Abstract

One example method of video processing includes implementing, by a processor, a decoder-side motion vector derivation (DMVD) scheme for motion vector refinement during a conversion between a current video block and a bitstream representation of the current video block by deriving parameters based on a deriving rule. The conversion may include compressing the current video block into the bitstream representation or uncompressing the bitstream representation into pixel values of the current video block.

Claims (40)

1. A method of processing video data, comprising:

obtaining a refined motion information for a current video block of a video by implementing a decoder-side motion vector derivation (DMVD) scheme for the current video block, wherein a symmetric motion vector difference (SMVD) mode is enabled for the current video block; and

performing a conversion between the current video block and a bitstream of the video using the refined motion information,

wherein the DMVD scheme includes a decoder-side motion vector refinement (DMVR) scheme, and/or a bi-directional optical flow (BDOF) scheme, and

(i) wherein, in the SMVD mode, the DMVD scheme is used to refine a motion vector difference (MVD) for the refined motion information by changing a motion vector (MV) precision or a MVD precision from N-pel precision to an M-pel precision, wherein N and M are equal to 1/16, ⅛, ¼, ½, 1, 2, 4, 8, or 16, or

(ii) wherein an Adaptive Motion Vector difference Resolution (AMVR) information is not signaled in the bitstream for a video block coded in the SMVD mode, and wherein the MV precision or the MVD precision for the refined motion information is derived according to a pre-defined value.

2. The method of claim 1 , further comprising:

determining, based on a field in the bitstream for the video including the current video block, whether to enable or disable the DMVD scheme for the current video block in the SMVD mode before the obtaining the refined motion information for the current video block.

3. The method of claim 1 , wherein the bitstream includes the MVD for the refined motion information, and wherein the MVD is decoded according to the SMVD mode and is further refined before being used to decode the current video block.

4. The method of claim 1 , wherein the M is less than or equal to the N.

5. The method of claim 1 , wherein the bitstream does not include a signaling for the MVD for the refined motion information in the SMVD mode, and wherein the MVD is generated using the DMVD scheme.

6. The method of claim 1 , wherein in case that the MV precision or the MVD precision is derived according to the pre-defined value, the MV precision or the MVD precision is ¼-pel precision.

7. The method of claim 1 , wherein the pre-defined value is signaled in a sequence, a picture, a tile group, a slice, a tile, a video data unit level in the bitstream.

8. The method of claim 1 , wherein the pre-defined value depends on a mode information or a motion information.

9. The method of claim 8 , wherein the mode information or the motion information includes an affine motion information or a non-affine motion information.

10. The method of claim 2 , wherein the MVD is not signaled in the bitstream in response to the DMVD scheme being enabled.

11. The method of claim 2 , wherein the field indicating whether the DMVD scheme is enabled or disabled is present in the bitstream for one or more motion vector (MV) precisions or motion vector difference (MVD) precisions.

12. The method of claim 11 , wherein the one or more MV precisions or MVD precisions include 1-pel and/or 4-pel precision.

13. The method of claim 2 ,

wherein the field indicating whether the DMVD scheme is enabled or disabled is signaled in the bitstream in response to a first picture order count distance (PocDis0) representing a first distance from a first reference picture (Ref0) of the current video block to a current picture being equal to a second picture order count distance (PocDis1) representing a second distance from the current picture to a second reference picture (Ref1) of the current video block, and

wherein one of the first and second reference picture precedes the current picture and the other of the first and second reference picture follows the current picture in a display order.

14. The method of claim 2 , wherein the DMVD scheme is enabled in the SMVD mode based on one of:

a coding information of the current video block and/or of one or more neighboring blocks;

a block dimensions of the current video block;

information related to reference pictures for the current video block, wherein information related to the reference pictures includes picture order count (POC) information; or

a signaling for a motion vector difference (MVD) information in the bitstream.

15. The method of claim 1 , wherein the conversion includes encoding the current video block into the bitstream.

16. The method of claim 1 , wherein the conversion includes decoding the current video block from the bitstream.

17. An apparatus for processing video data comprising a processor and a non-transitory memory with instructions thereon, wherein the instructions upon execution by the processor, cause the processor to:

obtain a refined motion information for a current video block of a video by implementing a decoder-side motion vector derivation (DMVD) scheme for the current video block wherein a symmetric motion vector difference (SMVD) mode is enabled for the current video block; and

perform a conversion between the current video block and a bitstream of the video using the refined motion information,

wherein the DMVD scheme includes a decoder-side motion vector refinement (DMVR) scheme, and/or a bi-directional optical flow (BDOF) scheme, and

(i) wherein, in the SMVD mode, the DMVD scheme is used to refine a motion vector difference (MVD) for the refined motion information by changing a motion vector (MV) precision or a MVD precision from N-pel precision to an M-pel precision, wherein N and M are equal to 1/16, ⅛, ¼, ½, 1, 2, 4, 8, or 16, or

(ii) wherein an Adaptive Motion Vector difference Resolution (AMVR) information is not signaled in the bitstream for a video block coded in SMVD mode, and wherein the MV precision or the MVD precision for the refined motion information is derived according to a pre-defined value.

18. A non-transitory computer-readable recording medium storing a bitstream which is generated by a method performed by a video processing apparatus, wherein the method comprises:

obtaining a refined motion information for a current video block of a video by implementing a decoder-side motion vector derivation (DMVD) scheme for the current video block wherein a symmetric motion vector difference (SMVD) mode is enabled for the current video block; and

generating the bitstream using the refined motion information,

wherein the DMVD scheme includes a decoder-side motion vector refinement (DMVR) scheme, and/or a bi-directional optical flow (BDOF) scheme, and

(i) wherein, in the SMVD mode, the DMVD scheme is used to refine a motion vector difference (MVD) for the refined motion information by changing a motion vector (MV) precision or a MVD precision from N-pel precision to an M-pel precision, wherein N and M are equal to 1/16, ⅛, ¼, ½, 1, 2, 4, 8, or 16, or

(ii) wherein an Adaptive Motion Vector difference Resolution (AMVR) information is not signaled in the bitstream for a video block coded in SMVD mode, and wherein the MV precision or the MVD precision for the refined motion information is derived according to a pre-defined value.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2021
From: ZHANG, LI; ZHANG, KAI; XU, JIZHENG
To: BYTEDANCE INC.
Reel/Frame 057172/0680 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2021
From: LIU, HONGBIN; WANG, YUE
To: BEIJING BYTEDANCE NETWORK TECHNOLOGY CO., LTD.
Reel/Frame 057172/0903 →
Priority Claims (2)
WO PCT/CN2019/075068 · Feb 14, 2019 · international
WO PCT/CN2019/082585 · Apr 13, 2019 · international
Continuity (2)
Continuation PCTCN2020075232 · Feb 14, 2020
Related Publication 20210377559A1 · Dec 2, 2021
Cited By (4)
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