Semiconductor device and method for fabricating the same

1. A method for fabricating a semiconductor device, comprising:

forming a lower structure including an interconnection;

forming a first contact plug coupled to the interconnection;

forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the lower structure;

forming an opening that penetrates the alternating stack and exposes the first contact plug;

forming a sacrificial plug including a void in the opening;

forming a contact hole that exposes the first contact plug by etching a portion of the sacrificial plug; and

forming a second contact plug in the contact hole,

wherein forming the sacrificial plug including the void in the opening includes:

forming a non-conformal layer that covers a top corner of the opening; and

forming a conformal layer that fills the opening over the non-conformal layer, wherein the conformal layer is formed with a void which is positioned inside the opening.

2. The method of claim 1 ,

wherein a material forming the conformal layer has increased step coverage over a material forming the non-conformal layer.

3. The method of claim 1 ,

wherein the non-conformal layer includes a first oxide and the conformal layer includes a second oxide, wherein the second oxide has increased step coverage over the first oxide.

4. The method of claim 1 ,

wherein the non-conformal layer includes plasma enhanced tetraethylorthosilicate (PETEOS).

5. A method for fabricating a semiconductor device, comprising:

forming a source structure including a first contact plug over a lower structure including an interconnection, wherein the first contact plug is coupled to the interconnection;

forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the source structure;

forming a vertical channel structure that penetrates a portion of the alternating stack;

forming a void-embedded sacrificial plug that is spaced apart from the vertical channel structure, penetrates the alternating stack, and is coupled to the first contact plug;

replacing a portion of the sacrificial layers with gate electrodes to surround the vertical channel structure;

forming a contact hole that exposes the first contact plug by etching a portion of the void-embedded sacrificial plug;

forming a pad contact hole that exposes an edge of one of the gate electrodes;

forming a contact plug in the contact hole; and

forming a gate contact plug in the pad contact hole,

wherein forming the void-embedded sacrificial plug includes:

forming an opening that is spaced apart from the vertical channel structure, penetrates the alternating stack, and exposes the first contact plug;

forming a non-conformal layer that covers a top corner of the opening; and

forming a conformal layer that fills the opening over the non-conformal layer, wherein the conformal layer is formed with a void which is positioned inside the opening.

6. The method of claim 5 ,

wherein a material forming the conformal layer has increased step coverage over a material forming the non-conformal layer.

7. The method of claim 5 ,

wherein the non-conformal layer includes a first oxide and the conformal layer includes a second oxide, wherein the second oxide has increased step coverage over the first oxide.

8. The method of claim 5 ,

wherein the non-conformal layer includes plasma enhanced tetraethylorthosilicate (PETEOS).

9. A method for fabricating a semiconductor device, comprising:

forming a source structure including a first contact plug over a lower structure including an interconnection, wherein the first contact plug is coupled to the interconnection;

forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the source structure;

forming a vertical channel structure that penetrates the alternating stack;

forming a hole-type opening that exposes the first contact plug and line-type openings that are disposed adjacent to the hole-type opening, the hole-type opening and the line-type openings being spaced apart from the vertical channel structure and penetrating the alternating stack;

forming a void-embedded sacrificial plug in the hole-type opening;

filling the line-type openings with void-free supporters;

replacing a portion of the sacrificial layers with gate electrodes to surround the vertical channel structure;

forming a contact hole that exposes the first contact plug by etching a portion of the void-embedded sacrificial plug;

forming a pad contact hole that exposes an edge of one of the gate electrodes;

forming a contact plug in the contact hole; and

forming a gate contact plug in the pad contact hole,

wherein forming the void-embedded sacrificial plug in the hole-type opening includes:

forming a non-conformal layer that covers a top corner of the hole-type opening; and

forming a conformal layer that fills the hole-type opening over the non-conformal layer, wherein the conformal layer is formed with a void which is positioned inside the hole-type opening.

10. The method of claim 9 ,

wherein a material forming the conformal layer has increased step coverage over a material forming the non-conformal layer.

11. The method of claim 9 ,

wherein the non-conformal layer includes a first oxide and the conformal layer includes a second oxide, wherein the second oxide has increased step coverage over the first oxide.

12. The method of claim 9 ,

wherein the non-conformal layer includes plasma enhanced tetraethylorthosilicate (PETEOS).

13. The method of claim 9 ,

wherein edges of the gate electrodes are formed in a stepped structure.

14. The method of claim 13 , further comprising:

forming a plurality of pillar-type supporters that penetrate the stepped structure.

15. A method, for fabricating a semiconductor device, comprising:

forming a source structure including a first contact plug over a lower structure including an interconnection, wherein the first contact plug is coupled to the interconnection;

forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the source structure;

forming a vertical channel structure that penetrates the alternating stack;

forming a hole-type opening that exposes the first contact plug and line-type openings that are disposed adjacent to the hole-type opening, the hole-type opening and the line-type openings being spaced apart from the vertical channel structure and penetrating the alternating stack;

forming a void-embedded sacrificial plug in the hole-type opening;

filling the line-type openings with void-free supporters;

replacing a portion of the sacrificial layers with gate electrodes to surround the vertical channel structure;

forming a contact hole that exposes the first contact plug by etching a portion of the void-embedded sacrificial plug;

forming a pad contact hole that exposes an edge of one of the gate electrodes;

forming a contact plug in the contact hole; and

forming a gate contact plug in the pad contact hole,

wherein forming the void-embedded sacrificial plug in the hole-type opening and filling the line-type openings with the void-free supporters includes:

forming a non-conformal layer that covers a top corner of the hole-type opening and top corners of the line-type openings;

forming a conformal layer that fills the hole-type opening and the line-type openings over the non-conformal layer and includes voids;

removing the non-conformal layer and the conformal layer from the top corners of the line-type openings to expose the voids of the line-type openings; and

filling the exposed voids of the line-type openings with a supporter material.

16. The method of claim 15 , wherein each of the non-conformal layer and the conformal layer includes silicon oxide, and

the non-conformal layer includes plasma enhanced tetraethylorthosilicate (PETEOS), and

the conformal layer includes silicon oxide that is formed by an Atomic Layer Deposition (ALD) process.