Semiconductor memory device and manufacturing method of semiconductor memory device
A semiconductor memory device and a manufacturing method of a semiconductor memory device are described. The semiconductor memory device includes a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked, a first channel structure penetrating the gate stack structure, a first contact structure connected to the first channel structure, the first contact structure extending onto the gate stack structure, a bit line disposed on the first contact structure and being in contact with the first contact structure, a tunnel insulating layer disposed between the first channel structure and the gate stack structure, a data storage layer disposed between the tunnel insulating layer and the gate stack structure, and a blocking insulating layer disposed between the data storage layer and the gate stack structure, the blocking insulating layer extending between the first contact structure and the gate stack structure.
1. A semiconductor memory device comprising:
a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked;
a first channel structure penetrating the gate stack structure;
a first contact structure connected to the first channel structure, the first contact structure extending onto the gate stack structure;
a bit line disposed on the first contact structure and being in contact with the first contact structure;
a tunnel insulating layer disposed between the first channel structure and the gate stack structure;
a data storage layer disposed between the tunnel insulating layer and the gate stack structure; and
a blocking insulating layer disposed between the data storage layer and the gate stack structure, the blocking insulating layer extending between the first contact structure and the gate stack structure,
wherein a distance between the bit line and the tunnel insulating layer is greater than a distance between the bit line and the blocking insulating layer.
2. The semiconductor memory device of claim 1 , wherein the first channel structure includes:
a core insulating layer extending in a stacking direction in which the interlayer insulating layers and the conductive patterns are stacked;
a doped semiconductor pattern disposed between the first contact structure and the core insulating layer; and
a channel layer surrounding the core insulating layer, the channel layer extending toward the bit line to be in contact with the doped semiconductor pattern.
3. The semiconductor memory device of claim 2 ,
wherein a distance between the bit line and the channel layer is greater than the distance between the blocking insulating layer and the bit line.
4. The semiconductor memory device of claim 2 ,
wherein the doped semiconductor pattern extends between the first contact structure and the tunnel insulating layer.
5. The semiconductor memory device of claim 2 ,
wherein the first contact structure is formed of a conductive material having an etch selectivity different from that of the doped semiconductor pattern.
6. The semiconductor memory device of claim 2 , wherein the first contact structure includes:
a metal layer disposed in a central region of the first contact structure; and
a conductive liner layer in contact with a surface of the metal layer and extending along a sidewall of the metal layer, wherein the surface of the metal layer faces the doped semiconductor pattern and the gate stack structure.
7. The semiconductor memory device of claim 6 ,
wherein the conductive liner layer includes titanium (Ti) and titanium nitride (TiN), includes titanium nitride (TiN), or includes titanium silicide (TiSi).
8. The semiconductor memory device of claim 1 , further comprising:
a second channel structure penetrating the gate stack structure; and
a second contact structure in contact with the second channel structure, the second contact structure extending to be in contact with the bit line.
9. The semiconductor memory device of claim 8 , wherein the conductive patterns include:
a word line surrounding the first channel structure and extending to surround the second channel structure;
a first select line disposed between the bit line and the word line, the first select line surrounding the first channel structure; and
a second select line disposed between the bit line and the word line, the second select line surrounding the second channel structure.
10. The semiconductor memory device of claim 9 , further comprising an isolation insulating layer disposed between the first select line and the second select line,
wherein the first contact structure and the second contact structure extend onto the gate stack structure in a direction moving away from the isolation insulating layer.
11. A method of manufacturing a semiconductor memory device, the method comprising:
forming channel holes penetrating a stack structure;
forming a blocking insulating layer including a vertical part disposed on a sidewall of each of the channel holes and a horizontal part extending along a top surface of the stack structure;
forming pillar structures respectively in the channel holes opened by the vertical part of the blocking insulating layer, wherein an upper end portion of each of the channel holes is opened;
forming a doped semiconductor layer including a first part filling the upper end portion of each of the channel holes and a second part extending from the first part, wherein the second part extends in a direction intersecting the first part to overlap with the stack structure;
forming contact holes respectively overlapping with the pillar structures by etching a portion of the doped semiconductor layer;
forming contact structures respectively filling the contact holes; and
removing the second part of the doped semiconductor layer.
12. The method of claim 11 , wherein the forming of the pillar structures includes:
sequentially forming a data storage layer, a tunnel insulating layer, and a channel layer on the blocking insulating layer;
forming a core insulating layer in a central region of each of the channel holes, which is opened by the channel layer, wherein the upper end portion of each of the channel holes is opened by the core insulating layer;
removing a portion of the channel layer and a portion of the tunnel insulating layer such that the data storage layer is exposed through the upper end portion of each of the channel holes; and
removing a portion of the data storage layer such that the horizontal part of the blocking insulating layer is exposed.
13. The method of claim 11 ,
wherein the forming of the contact holes is performed such that the first part of the doped semiconductor layer is exposed.
14. The method of claim 11 ,
wherein each of the contact holes extends in a direction intersecting the pillar structures to overlap with the stack structure.
15. The method of claim 11 ,
wherein each of the contact structures is made of a conductive material having an etch selectivity different from that of the doped semiconductor laver.
16. The method of claim 11 , wherein the forming of the contact structures includes:
forming a conductive liner layer in contact with the doped semiconductor layer along a surface of each of the contact holes; and
forming a metal layer filling a central region of each of the contact holes on the conductive liner layer.
17. The method of claim 16 ,
wherein the conductive liner layer includes titanium (Ti) and titanium nitride (TiN), includes titanium nitride (TiN), or includes titanium silicide (TiSi).
18. The method of claim 11 ,
wherein the removing of the second part of the doped semiconductor layer is performed such that the doped semiconductor layer is isolated into doped semiconductor patterns respectively overlapping with the pillar structures.
19. The method of claim 11 ,
wherein a portion of the first part of the doped semiconductor layer is exposed by removing the second part of the doped semiconductor layer.
20. The method of claim 11 ,
wherein the stack structure includes first material layers and second material layers, which are alternately stacked,
wherein the pillar structures include a first pillar structure and a second pillar structure, which penetrate the first material layers and the second material layers, and
wherein the contact structures include a first contact structure overlapping with the first pillar structure and a second contact structure overlapping with the second pillar structure.
21. The method of claim 20 , further comprising:
after the removing of the second part of the doped semiconductor layer,
forming an insulating layer covering the first and second contact structures;
forming a slit penetrating the insulating layer, the blocking insulating layer, and the first and second material layers;
replacing the second material layers with conductive patterns through the slit;
forming an isolation insulating layer penetrating at least one conductive pattern adjacent to the insulating layer among the conductive patterns between the first pillar structure and the second pillar structure;
removing a portion of the insulating layer such that the first and second contact structures are exposed; and
forming a bit line in contact with the first and second contact structures, the bit line extending onto a remaining portion of the insulating layer.