Device, system and method to provide line level tagging of data at a processor cache
Techniques and mechanisms for identifying tag information that describes data to be cached at a processor. In an embodiment, a memory controller services a memory access request from the processor, wherein the memory controller reads multiple chunks of data from a memory device, and determines first tag information which corresponds to the multiple chunks. One or more of the multiple chunks are sent to the processor in a response to the request. Based on the first tag information, the memory controller detects for a match—if any—between at least two tags. Where such a match is detected, the memory controller further indicates to the processor that second tag information corresponds to the one or more chunks. In another embodiment, the first tag information is more granular than the second tag information.
1. A memory controller comprising:
protocol circuitry to receive a request from a processor and, based on the request, to read data from an addressable location of a memory device, wherein the data comprises multiple chunks, and wherein the protocol circuitry is further to send one or more chunks of the multiple chunks to the processor in a response to the request;
tag identification circuitry, coupled to the protocol circuitry, to determine first tag information which corresponds to the data, wherein the first tag information provides a first granularity at which the multiple chunks each correspond to a respective tag; and
tag evaluation circuitry, coupled to the tag identification circuitry, to detect a match between at least two tags based on the first tag information;
wherein, based on the match, the protocol circuitry is to indicate to the processor that second tag information corresponds to the one or more chunks, wherein the second tag information provides a second granularity at which the one or more chunks each correspond to a respective tag, wherein the first granularity is more than the second granularity.
2. The memory controller of claim 1 , wherein the tag evaluation circuitry to detect the match comprises the tag evaluation circuitry to perform a first evaluation to determine that a first tag, provided to the memory controller by the processor, is equal to a second tag of the first tag information.
3. The memory controller of claim 2 , wherein the tag evaluation circuitry to detect the match further comprises:
the tag evaluation circuitry to perform a second evaluation, based on the first evaluation, to determine whether all other tags of the first tag information each match the first tag.
4. The memory controller of claim 1 , wherein the response omits one or more other chunks of the multiple chunks.
5. The memory controller of claim 1 , wherein the request is a first request, the addressable location is a first addressable location, the data is first data, and the multiple chunks are a first multiple chunks, wherein:
the protocol circuitry is further to read second data from a second addressable location of the memory device based on a second request from the processor, wherein the second data comprises a second multiple chunks;
the tag identification circuitry is further to determine third tag information which corresponds to the second data;
the tag evaluation circuitry is further to detect a mismatch between a first tag provided by the processor and a second tag of the third tag information; and
the protocol circuitry is further to send to the processor a second response to the second request, wherein the second response comprises a second one or more chunks of the second multiple chunks, wherein based on the mismatch, the second response further comprises an indication that the processor is to forego a write of the second one or more chunks to a cache of the processor.
6. The memory controller of claim 5 , wherein the second request is on behalf of a process executed with a core of the processor, wherein the core comprises the cache.
7. The memory controller of claim 6 , wherein the cache is a L1 cache of the core, wherein the indication is further to prevent a write of the one or more chunks to another cache of the processor.
8. A method at a memory controller, the method comprising:
based on a request from a processor:
reading data from an addressable location of a memory device, the data comprising multiple chunks; and
determining first tag information which corresponds to the data, wherein the first tag information provides a first granularity at which the multiple chunks each correspond to a respective tag;
detecting a match between at least two tags based on the first tag information;
sending to the processor one or more chunks of the multiple chunks in a response to the request; and
based on the match, indicating to the processor that second tag information corresponds to the one or more chunks, wherein the second tag information provides a second granularity at which the one or more chunks each correspond to a respective tag, wherein the first granularity is more than the second granularity.
9. The method of claim 8 , wherein detecting the match comprises performing a first evaluation to determine that a first tag, provided to the memory controller by the processor, is equal to a second tag of the first tag information.
10. The method of claim 9 , wherein detecting the match further comprises:
based on the first evaluation, performing a second evaluation to determine whether all other tags of the first tag information each match the first tag.
11. The method of claim 8 , wherein the response omits one or more other chunks of the multiple chunks.
12. The method of claim 8 , wherein the request is a first request, the addressable location is a first addressable location, the data is first data, and the multiple chunks are a first multiple chunks, the method further comprising:
based on a second request from the processor:
reading second data from a second addressable location of the memory device, the second data comprising a second multiple chunks; and
determining third tag information which corresponds to the second data;
detecting a mismatch between a first tag provided by the processor and a second tag of the third tag information; and
sending to the processor a second response to the second request, the second response comprising one or more chunks of the second multiple chunks, wherein based on the mismatch, the second response further comprises an indication that the processor is to forego a write of the one or more chunks to a cache of the processor.
13. The method of claim 12 , wherein the second request is on behalf of a process executed with a core of the processor, wherein the core comprises the cache.
14. The method of claim 13 , wherein the cache is a L1 cache of the core, wherein the indication is further to prevent a write of the one or more chunks to another cache of the processor.
15. A system comprising:
a processor;
a memory device;
a memory controller coupled to the processor and the memory device, the memory controller comprising:
protocol circuitry to receive a request from the processor and, based on the request, to read data from an addressable location of the memory device, wherein the data comprises multiple chunks, and wherein the protocol circuitry is further to send one or more chunks of the multiple chunks to the processor in a response to the request;
tag identification circuitry, coupled to the protocol circuitry, to determine first tag information which corresponds to the data, wherein the first tag information provides a first granularity at which the multiple chunks each correspond to a respective tag; and
tag evaluation circuitry, coupled to the tag identification circuitry, to detect a match between at least two tags based on the first tag information;
wherein, based on the match, the protocol circuitry is to indicate to the processor that second tag information corresponds to the one or more chunks, wherein the second tag information provides a second granularity at which the one or more chunks each correspond to a respective tag, wherein the first granularity is more than the second granularity; and
a display device coupled to the processor, the display device to display an image based on the one or more chunks.
16. The system of claim 15 , wherein the tag evaluation circuitry to detect the match comprises the tag evaluation circuitry to perform a first evaluation to determine that a first tag, provided to the memory controller by the processor, is equal to a second tag of the first tag information.
17. The system of claim 16 , wherein the tag evaluation circuitry to detect the match further comprises:
the tag evaluation circuitry to perform a second evaluation, based on the first evaluation, to determine whether all other tags of the first tag information each match the first tag.
18. The system of claim 15 , wherein the response omits one or more other chunks of the multiple chunks.
19. The system of claim 15 , wherein:
the request is a first request, the addressable location is a first addressable location, the data is first data, and the multiple chunks are a first multiple chunks;
the protocol circuitry is further to read second data from a second addressable location of the memory device based on a second request from the processor, wherein the second data comprises a second multiple chunks;
the tag identification circuitry is further to determine third tag information which corresponds to the second data;
the tag evaluation circuitry is further to detect a mismatch between a first tag provided by the processor and a second tag of the third tag information; and
the protocol circuitry is further to send to the processor a second response to the second request, wherein the second response comprises a second one or more chunks of the second multiple chunks, wherein based on the mismatch, the second response further comprises an indication that the processor is to forego a write of the second one or more chunks to a cache of the processor.
20. The system of claim 19 , wherein the second request is on behalf of a process executed with a core of the processor, wherein the core comprises the cache.