Shift register unit, gate driving circuit, display device, and driving method

1. A shift register unit, comprising a blanking input circuit, a blanking control circuit, a blanking coupling circuit, a display input circuit and an output circuit,

wherein the blanking input circuit is configured to charge a control node in response to a compensation selection control signal, and to maintain a level of the control node;

the blanking control circuit is configured to charge a first node, by using a first clock signal, under control of the first clock signal and the level of the control node;

the blanking coupling circuit is electrically connected to the control node, and is configured to control, by coupling, the level of the control node in response to the first clock signal;

the display input circuit is configured to charge the first node in response to a display input signal; and

the output circuit is configured to output a composite output signal to an output terminal under control of a level of the first node.

2. The shift register unit according to claim 1 , wherein the blanking input circuit comprises a first transistor and a first capacitor;

a gate electrode of the first transistor is connected to a compensation selection control terminal to receive the compensation selection control signal, a first electrode of the first transistor is connected to a blanking input signal terminal, and a second electrode of the first transistor is connected to the control node; and

a first electrode of the first capacitor is connected to the control node, and a second electrode of the first capacitor is connected to a first voltage terminal.

3. The shift register unit according to claim 2 , wherein the blanking control circuit comprises a second transistor and a third transistor;

a gate electrode of the second transistor is connected to the control node, a first electrode of the second transistor is connected to a first clock signal terminal to receive the first clock signal, and a second electrode of the second transistor is connected to a first electrode of the third transistor; and

a gate electrode of the third transistor is connected to the first clock signal terminal to receive the first clock signal, and a second electrode of the third transistor is connected to the first node.

4. The shift register unit according to claim 3 , wherein the blanking coupling circuit comprises a first coupling capacitor,

a first electrode of the first coupling capacitor is connected to the first clock signal terminal to receive the first clock signal, and a second electrode of the first coupling capacitor is connected to the control node.

5. The shift register unit according to claim 1 , wherein the display input circuit comprises a fourth transistor,

a gate electrode of the fourth transistor is connected to a display input signal terminal to receive the display input signal, a first electrode of the fourth transistor is connected to a second voltage terminal to receive a second voltage, and a second electrode of the fourth transistor is connected to the first node.

6. The shift register unit according to claim 1 , wherein the output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal, and the output circuit comprises a fifth transistor and a sixth transistor;

a gate electrode of the fifth transistor is connected to the first node, a first electrode of the fifth transistor is connected to a second clock signal terminal to receive a second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the fifth transistor is connected to the shift signal output terminal; and

a gate electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the second clock signal terminal to receive the second clock signal and the second clock signal is used as the composite output signal, and a second electrode of the sixth transistor is connected to the pixel scanning signal output terminal.

7. The shift register unit according to claim 6 , wherein the output circuit further comprises a second capacitor,

a first electrode of the second capacitor is connected to the first node, and a second electrode of the second capacitor is connected to the second electrode of the fifth transistor.

8. The shift register unit according to claim 1 , further comprising a first control circuit and a node control circuit,

wherein the output terminal comprises a shift signal output terminal and a pixel scanning signal output terminal, and the shift signal output terminal and the pixel scanning signal output terminal output the composite output signal;

the first control circuit is configured to control a level of a second node under control of the level of the first node; and

the node control circuit is configured to reset the first node, the shift signal output terminal, and the pixel scanning signal output terminal under control of the level of the second node.

9. The shift register unit according to claim 8 , wherein the first control circuit comprises a seventh transistor and a ninth transistor;

a gate electrode of the seventh transistor is connected to a first electrode of the seventh transistor and is configured to be connected to a third voltage terminal to receive a third voltage, and a second electrode of the seventh transistor is connected to the second node; and

a gate electrode of the ninth transistor is connected to the first node, a first electrode of the ninth transistor is connected to the second node, and a second electrode of the ninth transistor is connected to a fifth voltage terminal to receive a fifth voltage.

10. The shift register unit according to claim 9 , wherein the first control circuit further comprises an eighth transistor,

a gate electrode of the eighth transistor is connected to a first electrode of the eighth transistor and is configured to be connected to a fourth voltage terminal to receive a fourth voltage, and a second electrode of the eighth transistor is connected to a third node different from the second node.

11. The shift register unit according to claim 8 , wherein the node control circuit comprises a tenth transistor, an eleventh transistor, and a twelfth transistor;

a gate electrode of the tenth transistor is connected to the second node, a first electrode of the tenth transistor is connected to the first node, and a second electrode of the tenth transistor is connected to a fifth voltage terminal to receive a fifth voltage;

a gate electrode of the eleventh transistor is connected to the second node, a first electrode of the eleventh transistor is connected to the shift signal output terminal, and a second electrode of the eleventh transistor is connected to the fifth voltage terminal to receive the fifth voltage; and

a gate electrode of the twelfth transistor is connected to the second node, a first electrode of the twelfth transistor is connected to the pixel scanning signal output terminal, and a second electrode of the twelfth transistor is connected to a sixth voltage terminal to receive a sixth voltage.

12. The shift register unit according to claim 8 , further comprising a second control circuit and a third control circuit,

wherein the second control circuit is configured to control the level of the second node in response to the first clock signal; and

the third control circuit is configured to control the level of the second node in response to the display input signal.

13. The shift register unit according to claim 12 , wherein the second control circuit comprises a thirteenth transistor, and the third control circuit comprises a fourteenth transistor;

a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the second node, and a second electrode of the thirteenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and

a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the display input signal, a first electrode of the fourteenth transistor is connected to the second node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.

14. The shift register unit according to claim 12 , wherein the second control circuit comprises a thirteenth transistor and a seventeenth transistor, and the third control circuit comprises a fourteenth transistor;

a gate electrode of the thirteenth transistor is connected to a first clock signal terminal to receive the first clock signal, a first electrode of the thirteenth transistor is connected to the second node, and a second electrode of the thirteenth transistor is connected to a first electrode of the seventeenth transistor;

a gate electrode of the seventeenth transistor is electrically connected to the control node, and a second electrode of the seventeenth transistor is connected to a fifth voltage terminal to receive a fifth voltage; and

a gate electrode of the fourteenth transistor is connected to a display input signal terminal to receive the display input signal, a first electrode of the fourteenth transistor is connected to the second node, and a second electrode of the fourteenth transistor is connected to the fifth voltage terminal to receive the fifth voltage.

15. The shift register unit according to claim 8 , further comprising a display reset circuit and a total reset circuit,

wherein the display reset circuit is configured to reset the first node in response to a display reset signal; and

the total reset circuit is configured to reset the first node in response to a total reset signal.

16. A gate driving circuit, comprising a plurality of cascaded shift register units according to claim 1 .

17. The gate driving circuit according to claim 16 , further comprising a first sub-clock signal line, a second sub-clock signal line, a third sub-clock signal line, and a fourth sub-clock signal line,

wherein a (4n−3)th-stage shift register unit of the cascaded shift register units is connected to the first sub-clock signal line to receive a second clock signal,

a (4n−2)th-stage shift register unit of the cascaded shift register units is connected to the second sub-clock signal line to receive a second clock signal,

a (4n−1)th-stage shift register unit of the cascaded shift register units is connected to the third sub-clock signal line to receive a second clock signal,

a (4n)th-stage shift register unit of the cascaded shift register units is connected to the fourth sub-clock signal line to receive a second clock signal, and

n is an integer greater than zero.

18. The gate driving circuit according to claim 17 , further comprising a fifth sub-clock signal line and a sixth sub-clock signal line,

wherein each stage of the cascaded shift register units is connected to the fifth sub-clock signal line to receive a compensation selection control signal, and each stage of the cascaded shift register units is connected to the sixth sub-clock signal line to receive a total reset signal.

19. A display device, comprising the gate driving circuit according to claim 16 .

20. A driving method of the shift register unit according to claim 1 , comprising a display phase for one frame and a blanking phase for the frame,

during the display phase, causing the blanking input circuit to charge the control node in response to the compensation selection control signal and to maintain the level of the control node; and

during the blanking phase, causing the blanking control circuit to charge the first node, by using the first clock signal, under control of the first clock signal and the level of the control node, and causing the blanking coupling circuit to control, by coupling, the level of the control node in response to the first clock signal.