Multi-transistor stack architecture in a single vertical stack
Various implementations described herein relate to a method for manufacturing, or causing to be manufactured, multiple devices packaged within a single semiconductor die. The multiple devices may have first devices that are arranged in a first multi-transistor stack with a first P-N configuration. The multiple devices may have second devices that are arranged in a second multi-transistor stack with a second P-N configuration that is different than the first P-N configuration.
1. An apparatus comprising:
multiple devices packaged within a single semiconductor die, wherein:
the multiple devices include a first multi-transistor stack with a first P-N configuration, and
the multiple devices include a second multi-transistor stack with a second P-N configuration.
2. The apparatus of claim 1 , wherein the first multi-transistor stack and the second multi-transistor stack are arranged in a single vertical stack with a common-gate architecture.
3. The apparatus of claim 1 , wherein the first multi-transistor stack and the second multi-transistor stack are arranged in a single vertical stack.
4. The apparatus of claim 1 , wherein:
the first multi-transistor stack includes a first two-transistor stack, and
the second multi-transistor stack includes a second two-transistor stack.
5. The apparatus of claim 1 , wherein:
the first P-N configuration comprises a P-over-N configuration.
6. The apparatus of claim 1 , wherein:
the second P-N configuration comprises an N-over-P configuration.