Semiconductor imaging device having improved dark current performance

1. A method for forming an image sensor integrated chip, comprising:

forming a first photodetector region in a substrate;

forming a second photodetector region in the substrate;

forming a floating diffusion node in the substrate between the first photodetector region and the second photodetector region;

forming a pick-up well contact region in the substrate, wherein a first line intersects the floating diffusion node and the pick-up well contact region; and

forming one or more transistor gates on the substrate, wherein a second line that is perpendicular to the first line intersects the pick-up well contact region and the one or more transistor gates.

2. The method of claim 1 , wherein the first line and the second line are parallel to an upper surface of the substrate.

3. The method of claim 1 , further comprising:

forming an isolation structure within the substrate; and

forming the one or more transistor gates within a device region that is surrounded by the isolation structure, wherein a center of isolation structure is separated from a center of the floating diffusion node along a direction of the second line.

4. The method of claim 3 , wherein the isolation structure has an end that is between the first photodetector region and the second photodetector region.

5. The method of claim 1 , wherein the one or more transistor gates comprise one or more of a reset transistor gate, a select transistor gate, and a source-follower transistor gate.

6. The method of claim 1 , wherein the pick-up well contact region and the one or more transistor gates are entirely disposed along a same side of the first photodetector region.

7. An image sensor integrated chip, comprising:

a floating diffusion node disposed within a substrate;

a plurality of photodetectors disposed within the substrate and around the floating diffusion node as viewed in a plan-view;

a plurality of transfer transistor gates disposed on the substrate between the floating diffusion node and the plurality of photodetectors as viewed in the plan-view;

a pick-up well region disposed within the substrate, wherein a first line that is between adjacent ones of the plurality of transfer transistor gates extends through the pick-up well region as viewed in the plan-view; and

one or more transistor gates disposed on the substrate, wherein a second line that is perpendicular with the first line as viewed in the plan-view extends through the pick-up well region and the one or more transistor gates.

8. The image sensor integrated chip of claim 7 , wherein the one or more transistor gates comprise a reset transistor gate, a select transistor gate, and a source-follower transistor gate.

9. The image sensor integrated chip of claim 8 , wherein the one or more transistor gates are entirely disposed along a same side of the first line as viewed in the plan-view.

10. The image sensor integrated chip of claim 7 , further comprising:

one or more conductive interconnects coupled between the floating diffusion node and the one or more transistor gates.

11. The image sensor integrated chip of claim 7 , wherein the one or more transistor gates are electrically coupled to the floating diffusion node.

12. The image sensor integrated chip of claim 7 , further comprising:

an isolation structure disposed within the substrate and surrounding the one or more transistor gates.

13. The image sensor integrated chip of claim 12 , wherein a center of the isolation structure is off-centered from a center of the floating diffusion node along a second direction of the second line.

14. The image sensor integrated chip of claim 12 , wherein an entirety of the isolation structure is disposed along a same side of the first line.

15. An image sensor integrated chip, comprising:

a floating diffusion node disposed within a substrate;

a photodetector formation comprising a plurality of photodetectors disposed around the floating diffusion node as viewed in a plan-view;

a plurality of transfer transistor gates disposed between the floating diffusion node and the plurality of photodetectors as viewed in the plan-view;

a pick-up well region disposed within the substrate;

a plurality of transistor gates disposed on the substrate, wherein the plurality of transistor gates are disposed on a same side of the pick-up well region and are closest neighboring transistor gates to the pick-up well region, and

wherein the pick-up well region and the plurality of transistor gates are disposed along a same side of the photodetector formation and wherein the pick-up well region is closer to the floating diffusion node than the plurality of transistor gates in the plan-view.

16. The image sensor integrated chip of claim 15 , wherein the pick-up well region is separated from two closest neighboring ones of the plurality of photodetectors by substantially equal distances.

17. The image sensor integrated chip of claim 15 , further comprising:

a device isolation structure extending in a closed loop around the plurality of transistor gates.

18. The image sensor integrated chip of claim 17 , wherein the device isolation structure is off-centered from a center of the photodetector formation along a first direction and along a second direction perpendicular to the first direction as viewed in the plan-view.

19. The image sensor integrated chip of claim 17 , wherein the device isolation structure straddles a perimeter extending along outermost boundaries of the photodetector formation.

20. The image sensor integrated chip of claim 17 , further comprising:

a second floating diffusion node disposed within the substrate; and

a second photodetector formation comprising a second plurality of photodetectors disposed around the second floating diffusion node as viewed in the plan-view, wherein the device isolation structure continuously extends from below the photodetector formation to directly below the second photodetector formation as viewed in the plan-view.