IP Library › Granted Patent US 12,040,805
Granted Patent B2
US 12,040,805 · App. 17/853,148 · Granted Jul 16, 2024

Ring oscillator, random number generator including the same, and operation method of random number generator

Inventors: Hoyoung Shin (Gunpo-si, KR); Bora Kim (Hwaseong-si, KR); Junho Kim (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H03L7/0996G06F7/582H03K19/1737H03L7/0818H03L7/083H03L7/1077
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Quick Facts
Patent No.
US 12,040,805
App. No.
17/853,148
Granted
Jul 16, 2024
Kind
B2
Abstract

A random number generator includes a ring oscillator, an inversion selecting circuit, and controller. The ring oscillator includes an inverter chain having at least one inverter and generates an output signal. The inversion selecting circuit controlling a phase inverter configured to invert a signal of the inverter chain. The controller is configured to operate the inversion selecting circuit to provide an output of the first phase inverter to the inverter chain during a first operation mode to measure a frequency of the ring oscillator and operate the inversion selecting circuit to not provide the output of the phase inverter during a second operation mode for generating a random number.

Claims (22)

1. A random number generator comprising:

a ring oscillator comprising an inverter chain comprising at least one inverter and generating an output signal;

a first phase inverter receiving an input signal of the inverter chain; and

a buffer receiving the input signal,

wherein the random number generator provides an output of the first phase inverter to the inverter chain during a first operation mode to measure a frequency of the ring oscillator and provides an output of the buffer to the inverter chain during a second operation mode for generating a random number.

2. The random number generator of claim 1 , further comprising a first multiplexer, and the first multiplexer outputs a signal of the first phase inverter during the first operation mode and outputs a signal of the buffer during the second operation mode.

3. The random number generator of claim 1 , wherein the at least one inverter is a skewed inverter configured differently in size ratio of p-channel metal oxide semiconductor (PMOS) and n-channel metal oxide semiconductor (NMOS).

4. The random number generator of claim 1 , further comprising a counter that generates a collapse count by counting a number of pulses while the output signal of the ring oscillator stops after oscillating for a certain period due to a mismatch between the at least one inverter.

5. The random number generator of claim 4 , wherein the ring oscillator further comprises a second multiplexer for adjusting a range of the collapse count, and the second multiplexer selects an inverter constituting the inverter chain among a plurality of inverters different in rising delay time and falling delay time.

6. The random number generator of claim 4 , further comprises a calibration circuit that calibrates the collapse count when the collapse count is outside a preset range.

7. The random number generator of claim 4 , further comprising a comparator comparing the collapse count with a preset collapse count range upper limit value and a preset collapse count range lower limit value to calibrate the collapse count.

8. The random number generator of claim 4 , further comprises a calibration circuit that calibrates a range of the collapse count based on a first collapse count range corresponding to an initial operation of the ring oscillator and a second collapse count range corresponding to a random number generation operation of the ring oscillator.

9. The random number generator of claim 8 , wherein a lower limit value of the second collapse count range is less than a lower limit value of the first collapse count range, and an upper limit value of the second collapse count range is greater than an upper limit value of the first collapse count range.

10. The random number generator of claim 1 , further comprises a calibration circuit, wherein the output signal of the ring oscillator maintains oscillation in the first operation mode, and the calibration circuit adjusts a frequency of the output signal by comparing the output signal with a reference clock signal.

11. The random number generator of claim 1 , wherein the ring oscillator further comprises a third multiplexer for adjusting a frequency of the output signal, and the third multiplexer is configured to select a number of inverters constituting the inverter chain by receiving outputs of inverters constituting the inverter chain.

12. A ring oscillator comprising:

an inverter chain including a plurality of inverters;

a first phase inverter receiving an input signal of the inverter chain; and

a buffer receiving the input signal,

wherein the ring oscillator provides an output of the first phase inverter to the inverter chain during a first operation mode to measure a frequency of the ring oscillator and provides an output of the buffer to the inverter chain during a second operation mode to generate a random number.

13. The ring oscillator of claim 12 , further comprising a multiplexer selecting one of a plurality of inverters different in rising delay time and falling delay time to adjust a range of a collapse count used to generate the random number.

14. The ring oscillator of claim 12 , further comprising a calibration circuit, wherein an output signal of the ring oscillator maintains oscillation in the first operation mode, and the calibration circuit adjusts a frequency of the output signal by comparing the output signal with a reference clock signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2022
From: SHIN, HOYOUNG; KIM, BORA; KIM, JUNHO
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 060356/0161 →
Priority Claims (1)
KR 10-2021-0091690 · Jul 13, 2021 · national
Continuity (1)
Related Publication 20230019282A1 · Jan 19, 2023