Three-dimensional memory device with ferroelectric material

1. A memory device comprising:

a first layer stack over a substrate, the first layer stack comprising a first source/drain layer, a second source/drain layer over the first source/drain layer, and a first dielectric layer between the first source/drain layer and the second source/drain layer;

an isolation layer over the first layer stack;

a second layer stack over the isolation layer, the second layer stack comprising a third source/drain layer, a fourth source/drain layer over the third source/drain layer, and a second dielectric layer between the third source/drain layer and the fourth source/drain layer;

a first gate electrode extending through the first layer stack, the isolation layer, and the second layer stack, the first gate electrode being an electrically conductive material;

a first channel layer embedded in the first dielectric layer between the first source/drain layer and the second source/drain layer, the first channel layer extending along a first sidewall of the first layer stack facing the first gate electrode;

a second channel layer embedded in the second dielectric layer between the third source/drain layer and the fourth source/drain layer, wherein the second channel layer extends along a second sidewall of the second layer stack facing the first gate electrode, wherein the first channel layer is spaced apart from the second channel layer; and

a ferroelectric layer between the first gate electrode and the first layer stack and between the first gate electrode and the second layer stack, wherein the ferroelectric layer contacts and extends along sidewalls of the first gate electrode.

2. The memory device of claim 1 , wherein the ferroelectric layer contacts and extends along a first sidewall of the first source/drain layer facing the first gate electrode, and a second sidewall of the second source/drain layer facing the first gate electrode.

3. The memory device of claim 2 , wherein the ferroelectric layer further contacts and extends along a sidewall of the first channel layer facing the first gate electrode.

4. The memory device of claim 3 , wherein the ferroelectric layer further contacts and extends along a sidewall of the isolation layer facing the first gate electrode.

5. The memory device of claim 1 , wherein the ferroelectric layer extends continuously from the first sidewall of the first layer stack to the second sidewall of the second layer stack.

6. The memory device of claim 1 , wherein the first channel layer and the second channel layer are a same metal oxide material.

7. The memory device of claim 6 , wherein the first source/drain layer, the second source/drain layer, the third source/drain layer, and the fourth source/drain layer are a same metal material.

8. The memory device of claim 1 , wherein the first dielectric layer and the second dielectric layer are a same material, wherein the isolation layer is a different material than the first dielectric layer.

9. A memory device comprising:

a first layer stack and a second layer stack over a substrate, wherein the first layer stack is between the substrate and the second layer stack, wherein each of the first layer stack and the second layer stack comprises a first metal layer, a second metal layer over the first metal layer, and a first dielectric material between the first metal layer and the second metal layer, wherein the first metal layer and the second metal layer are source/drain layers of a transistor of a respective memory cell;

a second dielectric material between the first layer stack and the second layer stack;

a gate electrode extending through the first layer stack, the second dielectric material, and the second layer stack;

a ferroelectric material contacting and extending along sidewalls of the gate electrode, wherein the ferroelectric material is between the gate electrode and the first layer stack and between the gate electrode and the second layer stack; and

a channel material, wherein a first portion of the channel material is between the ferroelectric material and the first dielectric material of the first layer stack, wherein a second portion of the channel material is between the ferroelectric material and the first dielectric material of the second layer stack, wherein the first portion of the channel material is separated from the second portion of the channel material.

10. The memory device of claim 9 , wherein the ferroelectric material contacts and extends along the first portion of the channel material and the second portion of the channel material.

11. The memory device of claim 10 , wherein the ferroelectric material extends continuously from an upper surface of the second layer stack distal from the substrate to a lower surface of the first layer stack facing the substrate.

12. The memory device of claim 9 , wherein the first dielectric material and the second dielectric material are different materials.

13. The memory device of claim 9 , wherein the channel material is a metal oxide.

14. The memory device of claim 9 , wherein the first metal layer and the second metal layer are a same metal material.

15. The memory device of claim 9 , wherein the gate electrode is an electrically conductive material.

16. A memory device comprising:

a first layer stack over a substrate;

an isolation layer over the first layer stack;

a second layer stack over the isolation layer, wherein each of the first layer stack and the second layer stack comprises a first metal layer, a second metal layer over the first metal layer, and a dielectric layer between the first metal layer and the second metal layer, wherein the first metal layer and the second metal layer are a same metal material;

a gate electrode extending through the first layer stack, the isolation layer, and the second layer stack;

a channel material, wherein a first portion of the channel material is between the first metal layer of the first layer stack and the second metal layer of the first layer stack, and a second portion of the channel material is between the first metal layer of the second layer stack and the second metal layer of the second layer stack, wherein a sidewall of the first portion of the channel material is flush with a sidewall of the first metal layer of the first layer stack facing the gate electrode; and

a ferroelectric material between the gate electrode and the channel material, wherein the ferroelectric material contacts and extends along sidewalls of the gate electrode.

17. The memory device of claim 16 , wherein the first metal layer and the second metal layer are source/drain layers of a transistor of a respective memory cell.

18. The memory device of claim 17 , wherein the first portion of the channel material is spaced apart from the second portion of the channel material.

19. The memory device of claim 17 , wherein the sidewall of the first portion of the channel material is in contact with the ferroelectric material.

20. The memory device of claim 17 , wherein a sidewall of the second portion of the channel material is flush with a sidewall of the first metal layer of the second layer stack facing the gate electrode.