Ferroelectric random access memory device with a three-dimensional ferroelectric capacitor

1. A method of forming a semiconductor device, the method comprising:

forming a transistor over a substrate;

forming a first dielectric layer over the transistor;

forming a first via in the first dielectric layer, the first via electrically coupled to the transistor; and

forming a ferroelectric capacitor over the first dielectric layer, wherein forming the ferroelectric capacitor comprises:

forming a bottom electrode over the first dielectric layer, the bottom electrode protruding above an upper surface of the first dielectric layer distal from the substrate, the bottom electrode electrically coupled to the first via;

forming a ferroelectric film over the bottom electrode and over the first dielectric layer;

forming a top electrode layer over the ferroelectric film; and

removing first portions of the top electrode layer from an upper surface of the ferroelectric film facing away from the substrate, wherein after the removing, second portions of the top electrode layer remain and extend along sidewalls of the ferroelectric film.

2. The method of claim 1 , wherein removing the first portions of the top electrode layer comprises performing an anisotropic etching process to remove the first portions of the top electrode layer.

3. The method of claim 2 , wherein after removing the first portions of the top electrode layer, the upper surface of the ferroelectric film is exposed by the top electrode layer.

4. The method of claim 3 , wherein after removing the first portions of the top electrode layer, the ferroelectric film extends along the upper surface of the first dielectric layer, and extends laterally further from the bottom electrode than the second portions of the top electrode layer.

5. The method of claim 3 , further comprising, after removing the first portions of the top electrode layer:

forming a via over and contacting the upper surface of the ferroelectric film.

6. The method of claim 5 , wherein the via is formed of a material different from that of the top electrode layer.

7. The method of claim 2 , further comprising, after forming the top electrode layer and before removing the first portions of the top electrode layer:

forming a patterned mask layer over the top electrode layer and over the bottom electrode, wherein the anisotropic etching process is performed using the patterned mask layer as an etching mask.

8. The method of claim 7 , wherein a first width of the patterned mask layer, measured between opposing sidewalls of the patterned mask layer, is formed to be the same as a second width of the top electrode layer measured between opposing sidewalls of the top electrode layer.

9. The method of claim 1 , wherein forming the bottom electrode comprises:

forming a dummy dielectric layer over the first dielectric layer;

forming a conductive pillar in the dummy dielectric layer; and

removing the dummy dielectric layer after forming the conductive pillar, wherein the conductive pillar becomes the bottom electrode after removing the dummy dielectric layer.

10. The method of claim 9 , wherein the conductive pillar has a polygon-shaped cross-section.

11. A method of forming a semiconductor device, the method comprising:

forming a transistor over a substrate;

forming a first dielectric layer over the transistor;

forming a first via in the first dielectric layer, the first via electrically coupled to the transistor;

forming a dummy dielectric layer over the first dielectric layer;

forming a conductive pillar in the dummy dielectric layer;

removing the dummy dielectric layer to expose the conductive pillar;

after removing the dummy dielectric layer, forming a ferroelectric layer along sidewalls of the conductive pillar and along a top surface of the conductive pillar;

forming a top electrode layer over the ferroelectric layer; and

performing an anisotropic etching process to remove first portions of the top electrode layer from an upper surface of the ferroelectric layer facing away from the substrate, wherein after the anisotropic etching process, second portions of the top electrode layer remain and extend along sidewalls of the conductive pillar.

12. The method of claim 11 , further comprising, after the anisotropic etching process:

forming a second dielectric layer over the first dielectric layer around the conductive pillar;

forming a third dielectric layer over the second dielectric layer; and

forming a second via in the third dielectric layer, wherein the second via is over and electrically coupled to the second portions of the top electrode layer.

13. The method of claim 12 , further comprising:

forming a third via in the second dielectric layer laterally adjacent to the conductive pillar; and

forming a fourth via in the third dielectric layer, wherein the fourth via is over and electrically coupled to the third via, wherein the second via is formed to be wider than the fourth via.

14. The method of claim 11 , wherein after the anisotropic etching process, the ferroelectric layer extends along an upper surface of the first dielectric layer beyond exterior sidewalls of the second portions of the top electrode layer facing away from the conductive pillar.

15. The method of claim 11 , further comprising, after forming the top electrode layer and before performing the anisotropic etching process, forming a patterned mask on the top electrode layer directly over the conductive pillar, wherein the anisotropic etching process further removes portions of the ferroelectric layer that extend beyond lateral extents of the patterned mask.

16. A semiconductor device comprising:

a transistor over a substrate;

a first dielectric layer over the transistor;

a bottom electrode protruding above an upper surface of the first dielectric layer distal from the substrate;

a ferroelectric layer around the bottom electrode, wherein the ferroelectric layer contacts and extends along sidewalls of the bottom electrode and along an upper surface of the bottom electrode distal from the substrate; and

a top electrode around the ferroelectric layer, wherein the top electrode comprises a first electrically conductive material that contacts and extends along sidewalls of the ferroelectric layer, and comprises a second electrically conductive material that contacts and extends along an upper surface of the ferroelectric layer distal from the substrate, wherein the first electrically conductive material and the second electrically conductive material are different materials.

17. The semiconductor device of claim 16 , further comprising:

a second dielectric layer over the first dielectric layer and around the bottom electrode, wherein an upper surface of the second dielectric layer distal from the substrate is level with the upper surface of the ferroelectric layer.

18. The semiconductor device of claim 17 , further comprising:

a third dielectric layer over the second dielectric layer; and

a via in the third dielectric layer, wherein the via is over and electrically coupled to the top electrode.

19. The semiconductor device of claim 18 , wherein the via physically contacts the ferroelectric layer and the top electrode.

20. The semiconductor device of claim 16 , further comprising:

a second dielectric layer over the first dielectric layer and around the bottom electrode, wherein an upper surface of the second dielectric layer distal from the substrate is further from the substrate than an upper surface of the top electrode distal from the substrate.