Display panel and display device

1. A display panel, comprising a plurality of light-emitting devices arranged in an array and a pixel driving circuit configured to drive the light-emitting devices to emit light, wherein the pixel driving circuit comprises:

a first initialization transistor configured to input an initialization signal to a first node under control of a first scan signal;

a switching transistor configured to input a data signal to a second node under control of a second scan signal;

a driving transistor configured to drive the light-emitting devices to emit light under control of potentials of the first node and the second node;

a compensation transistor connected to the driving transistor through the first node and a third node, and configured to compensate a threshold voltage of the driving transistor under control of a third scan signal;

a second initialization transistor configured to input the initialization signal to an anode of the light-emitting devices under control of the third scan signal;

a first light-emitting control transistor connected to the driving transistor through the second node, and configured to conduct a current from a power supply high-potential signal line to the driving transistor under control of a light-emitting control signal;

a second light-emitting control transistor connected to the driving transistor through the third node, and configured to conduct a current from the driving transistor to the anode of the light-emitting devices under control of the light-emitting control signal; and

a storage capacitor, connected to the driving transistor through the first node, connected to the power supply high-potential signal line through a fourth node, and configured to store the data signal;

wherein the compensation transistor, the first initialization transistor, and the second initialization transistor are oxide transistors, and the switching transistor, the driving transistor, the first light-emitting control transistor, and the second light-emitting control transistor are low-temperature polysilicon transistors;

wherein the display panel comprises a substrate, a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a first source-drain layer, and a second source-drain layer, stacked from bottom to top, the first semiconductor layer forms polysilicon active layers of each of the low-temperature polysilicon transistors, and the second semiconductor layer forms oxide active layers of each of the oxide transistors;

wherein the first metal layer is patterned to form a first electrode plate of the storage capacitor, and the second metal layer is patterned to form a second electrode plate of the storage capacitor; and

wherein the first source-drain layer is patterned to form the power supply high-potential signal line, the second source-drain layer is patterned to form a first blocking member, the first blocking member is connected to the power supply high-potential signal line, and a projection of the first blocking member on the first metal layer covers at least a part of an area of the first electrode plate of the storage capacitor.

2. The display panel according to claim 1 , wherein the compensation transistor, the first initialization transistor, and the second initialization transistor are N-type transistors, and the switching transistor, the driving transistor, the first light-emitting control transistor, and the second light-emitting control transistor are P-type transistors.

3. The display panel according to claim 1 , wherein a projection of the polysilicon active layers on the substrate at least partially overlaps a projection of the oxide active layers on the substrate.

4. The display panel according to claim 1 , wherein the first metal layer is patterned to form a top gate of each of the oxide transistors, and the oxide active layers form a channel region of each of the oxide transistors, the second metal layer is patterned to form a bottom gate of each of the oxide transistors, and a projection of the channel region on the substrate falls within a projection range of a corresponding bottom gate on the substrate.

5. The display panel according to claim 1 , wherein a projection of the first blocking member on the oxide active layers covers a channel region of the compensation transistor and a channel region of the first initialization transistor.

6. The display panel according to claim 1 , wherein the second source-drain layer is patterned to form a second blocking member, the second blocking member is connected to the second light-emitting control transistor and the anode of the light-emitting devices, and a projection of the oxide active layers covers a channel region of the second initialization transistor.

7. A display device, comprising:

a first initialization transistor configured to input an initialization signal to a first node under control of a first scan signal;

a switching transistor configured to input a data signal to a second node under control of a second scan signal;

a driving transistor configured to drive a light-emitting device to emit light under control of potentials of the first node and the second node; and

a second initialization transistor configured to input an initialization signal to an anode of the light-emitting device under control of a third scan signal;

wherein the first initialization transistor and the second initialization transistor are oxide transistors, and the switching transistor and the second initialization transistor are different types of transistors;

wherein the display device comprises a substrate, a first semiconductor layer, a first metal layer, a second metal layer, a second semiconductor layer, a third metal layer, a first source-drain layer, and a second source-drain layer, stacked from bottom to top, the first semiconductor layer forms polysilicon active layers of the low-temperature polysilicon transistor, and the second semiconductor layer forms oxide active layers of the oxide transistors;

wherein the display device further comprises a storage capacitor, the storage capacitor is connected to the driving transistor through the first node, is connected to a power supply high-potential signal line through a fourth node, and is configured to store the data signal, the first metal layer is patterned to form a first electrode plate of the storage capacitor, and the second metal layer is patterned to form a second electrode plate of the storage capacitor; and

wherein the first source-drain layer is patterned to form the power supply high-potential signal line, the second source-drain layer is patterned to form a first blocking member, the first blocking member is connected to the power supply high-potential signal line, and a projection of the first blocking member on the first metal layer covers at least a part of an area of the first electrode plate of the storage capacitor.

8. The display device according to claim 7 , wherein the switching transistor is a low-temperature poly silicon transistor.

9. The display device according to claim 8 , wherein the switching transistor is a P-type transistor, and the first initialization transistor and the second initialization transistor are N-type transistors.

10. The display device according to claim 7 , wherein a projection of the polysilicon active layers on the substrate at least partially overlaps a projection of the oxide active layers on the substrate.

11. The display device according to claim 7 , wherein the second metal layer is patterned to form a bottom gate of each of the oxide transistors, the third metal layer is patterned to form a top gate of each of the oxide transistors, the oxide active layers form a channel region of each of the oxide transistors, and a projection of the channel region on the substrate falls within a projection range of a corresponding bottom gate on the substrate.

12. The display device according to claim 7 , wherein a projection of the first blocking member on the oxide active layers covers a channel region of the first initialization transistor.

13. The display device according to claim 7 , further comprising:

a first light-emitting control transistor connected to the driving transistor through the second node, and configured to conduct a current from a power supply high-potential signal line to the driving transistor under control of a light-emitting control signal; and

a second light-emitting control transistor connected to the driving transistor through a third node, and configured to conduct a current from the driving transistor to the anode of the light-emitting device under control of the light-emitting control signal;

wherein the driving transistor, the first light-emitting control transistor, and the second light-emitting control transistor are polysilicon transistors.

14. The display device according to claim 13 , wherein the second source-drain layer is patterned to form a second blocking member, the second blocking member is connected to the second light-emitting control transistor and the anode of the light-emitting device, and a projection of the oxide active layers covers a channel region of the second initialization transistor.