Processing unit reset by a virtual function bypassing a host driver
A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.
1. A method comprising:
detecting a reset condition at a virtual function of a virtual machine executing at a processing system; and
in response to detecting the reset condition, a local system management unit (SMU) of a processing unit initiating a reset sequence for a processing portion of the processing unit associated with the virtual function, the initiating bypassing a host driver of the processing system.
2. The method of claim 1 , wherein the reset sequence includes a handshake between the local SMU and a device driver of the virtual machine.
3. The method of claim 1 , wherein the initiating bypasses a hypervisor of the processing system.
4. The method of claim 1 , wherein the processing unit comprises a plurality of semiconductor dies, and wherein the processing portion of the processing unit comprises one of the plurality of semiconductor dies.
5. The method of claim 1 , wherein the processing unit is spatially partitioned into a plurality of processing portions comprising the processing portion.
6. The method of claim 4 , wherein the reset sequence comprises a reset sequence to reset the one of the plurality of semiconductor dies independent of resetting other semiconductor dies of the plurality of semiconductor dies.
7. The method of claim 5 , wherein each of the plurality of processing portions is assigned to a different one of a plurality of virtual functions comprising the virtual function.
8. A non-transitory computer readable medium tangibly embodying a set of instructions to manipulate a processor, the instructions comprising instructions to:
in response to detecting a reset condition at a virtual function of a virtual machine, initiate a reset sequence for a processing portion of a processing unit; and
responsive to initiating the reset sequence, execute a handshake between a local system management unit (SMU) of the processing unit and a local device driver of the virtual machine.
9. The non-transitory computer readable medium of claim 8 , wherein the reset sequence omits a handshake between the virtual function and a host driver of a processing system.
10. The non-transitory computer readable medium of claim 8 , wherein the processing unit comprises a graphics processing unit (GPU).
11. The non-transitory computer readable medium of claim 8 , wherein the reset condition comprises a detected error at the processing portion of the processing unit.
12. The non-transitory computer readable medium of claim 10 , wherein the GPU comprises a plurality of GPU chiplets, and wherein the processing portion corresponds to one of the plurality of GPU chiplets.
13. The non-transitory computer readable medium of claim 12 , wherein the processing portion comprises a render engine assigned to the virtual machine.
14. A processing system, comprising:
a processing unit; and
a processor to execute a virtual machine and a virtual function associated with the virtual machine, wherein in response to detecting a reset condition, a local system management unit (SMU) of the processing unit initiates a reset sequence for a processing portion of the processing unit associated with the virtual function, the reset sequence bypassing a host driver of the processing system.
15. The processing system of claim 14 , wherein the reset sequence includes a handshake between the local SMU and a device driver of the virtual machine.
16. The processing system of claim 14 , wherein the processing unit comprises a plurality of semiconductor dies, and wherein the processing portion of the processing unit comprises one of the plurality of semiconductor dies.
17. The processing system of claim 14 , wherein the processing unit is spatially partitioned into a plurality of processing portions.
18. The processing system of claim 15 , wherein the reset sequence bypasses a hypervisor of the processing system.
19. The processing system of claim 16 , wherein the reset sequence comprises a reset sequence to reset the one of the plurality of semiconductor dies independent of other semiconductor dies of the plurality of semiconductor dies.
20. The processing system of claim 17 , wherein each of the plurality of processing portions is assigned to a different one of a plurality of virtual functions.