Package having bonding layers
A package includes a carrier substrate, a first die, and a second die. The first die includes a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer. The first bonding layer is fusion bonded to the carrier substrate. The second die includes a third bonding layer. The third bonding layer is hybrid bonded to the second bonding layer of the first die.
1. A package, comprising:
a carrier substrate;
a first die comprising a first bonding layer, a second bonding layer opposite to the first bonding layer, and an alignment mark embedded in the first bonding layer, wherein the first bonding layer is fusion bonded to the carrier substrate; and
a second die comprising a third bonding layer, wherein the third bonding layer is hybrid bonded to the second bonding layer of the first die, and the first die is located between the carrier substrate and the second die.
2. The package of claim 1 , wherein the carrier substrate comprises semiconductor materials.
3. The package of claim 1 , wherein the second bonding layer and the third bonding layer respectively comprises a dielectric layer and a plurality of bonding pads embedded in the dielectric layer, the dielectric layer of the second bonding layer is hybrid bonded to the dielectric layer of the third bonding layer, and the bonding pads of the second bonding layer are hybrid bonded to and are aligned with the corresponding bonding pads of the third bonding layer.
4. The package of claim 3 , wherein the first die further comprises:
a semiconductor substrate;
an interconnection structure over the semiconductor substrate;
a passivation layer over the interconnection structure;
a plurality of bonding vias penetrating through the passivation layer and electrically connecting the interconnection structure and the bonding pads of the second bonding layer; and
an insulating layer surrounding the semiconductor substrate, the interconnection structure, and the passivation layer, wherein the second bonding layer is stacked on the passivation layer, the bonding vias, and the insulating layer.
5. The package of claim 4 , wherein the alignment mark is located directly on the insulating layer.
6. The package of claim 4 , wherein the first bonding layer comprises a first sub-layer and a second sub-layer, the first sub-layer is attached to the insulating layer and the semiconductor substrate, the second sub-layer is attached to the carrier substrate, and the alignment mark is embedded in the first sub-layer.
7. The package of claim 3 , wherein the second die further comprises:
a semiconductor substrate having a plurality of through semiconductor vias (TSV) embedded therein;
an interconnection structure over the semiconductor substrate and electrically connected to the TSVs;
a passivation layer over the interconnection structure;
a plurality of bonding vias penetrating through the passivation layer and electrically connecting the interconnection structure and the bonding pads of the third bonding layer; and
an insulating layer surrounding the semiconductor substrate, the interconnection structure, the passivation layer, and the third bonding layer.
8. The package of claim 7 , wherein the second die further comprises a plurality of through insulating vias (TIVs) penetrating through the insulating layer.
9. A package, comprising:
a carrier substrate;
a first die comprising a first bonding layer and a second bonding layer opposite to the first bonding layer, wherein the first bonding layer is fusion bonded to the carrier substrate, the second bonding layer comprises a first sub-layer and a second sub-layer, the first sub-layer is hybrid bonded to the second sub-layer; and
a second die comprising a third bonding layer, wherein the third bonding layer is hybrid bonded to the second sub-layer of the second bonding layer of the first die, and the first die is located between the carrier substrate and the second die.
10. The package of claim 9 , wherein the carrier substrate comprises semiconductor materials.
11. The package of claim 9 , wherein the first sub-layer, the second sub-layer, and the third bonding layer respectively comprises a dielectric layer and a plurality of bonding pads embedded in the dielectric layer, the dielectric layer of the first sub-layer is hybrid bonded to the dielectric layer of the second sub-layer, the bonding pads of the first sub-layer are hybrid bonded to and are aligned with the corresponding bonding pads of the second sub-layer, the dielectric layer of the second sub-layer is hybrid bonded to the dielectric layer of the third bonding layer, and the bonding pads of the second sub-layer are hybrid bonded to and are aligned with the corresponding bonding pads of the third bonding layer.
12. The package of claim 11 wherein the first die further comprises:
a semiconductor substrate;
an interconnection structure over the semiconductor substrate;
a passivation layer over the interconnection structure;
a plurality of bonding vias penetrating through the passivation layer and electrically connecting the interconnection structure and the bonding pads of the first sub-layer; and
an insulating layer surrounding the semiconductor substrate, the interconnection structure, the passivation layer, and the first sub-layer.
13. The package of claim 12 , wherein the first die further comprises an alignment mark embedded in the second sub-layer, and the alignment mark is directly in contact with the insulating layer.
14. The package of claim 11 , wherein the second die further comprises:
a semiconductor substrate having a plurality of through semiconductor vias (TSV) embedded therein;
an interconnection structure over the semiconductor substrate;
a passivation layer over the interconnection structure;
a plurality of bonding vias penetrating through the passivation layer and electrically connecting the interconnection structure and the bonding pads of the third bonding layer; and
an insulating layer surrounding the semiconductor substrate, the interconnection structure, the passivation layer, and the third bonding layer.
15. The package of claim 14 , wherein the second die further comprises a plurality of through insulating vias (TIVs) penetrating through the insulating layer.
16. A package, comprising:
a carrier substrate;
a first die disposed on the carrier substrate, comprising:
a semiconductor substrate;
a first bonding layer sandwiched between the semiconductor substrate and the carrier substrate, wherein the first bonding layer extends beyond a span of the semiconductor substrate; and
a second bonding layer disposed over the semiconductor substrate opposite to the first bonding layer, wherein the second bonding layer comprises a first sub-layer and a second sub-layer bonded to the first sub-layer, and the second sub-layer extends beyond a span of the semiconductor substrate; and
a second die comprising a third bonding layer, wherein the third bonding layer is bonded to the second sub-layer of the second bonding layer of the first die, and the first die is located between the carrier substrate and the second die.
17. The package of claim 16 , wherein sidewalls of the first sub-layer are aligned with sidewalls of the semiconductor substrate.
18. The package of claim 16 , wherein the first die further comprises an insulating layer laterally surrounding the semiconductor substrate, and the insulating layer is sandwiched between the second sub-layer and the first bonding layer.
19. The package of claim 18 , wherein the first die further comprises an alignment mark embedded in the second sub-layer, and the alignment mark is directly in contact with the insulating layer.
20. The package of claim 16 , wherein the carrier substrate comprises semiconductor materials.