Semiconductor memory device and a method of fabricating the same

1. A semiconductor memory device, comprising:

a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and

a bit line that vertically extends on one side of the stack structure,

wherein the word line includes:

a first conductive line that extends in a first direction; and

a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction,

wherein the channel layer is on the gate electrode,

wherein the bit line includes a connection part electrically connected to the channel layer, and

wherein a first portion of the channel layer is connected to the connection part, the first portion being sandwiched between the connection part and the gate electrode,

wherein the gate electrode includes a plurality of gate electrodes that protrude in the second direction from the first conductive line, and the word line has a comb shape.

2. The semiconductor memory device of claim 1 , wherein the channel layer is on a top surface, a bottom surface, and one end of the gate electrode.

3. The semiconductor memory device of claim 1 , wherein

the channel layer has a hollow internal space, and

the gate electrode is disposed in the internal space of the channel layer.

4. The semiconductor memory device of claim 1 , further comprising a gate dielectric layer between the channel layer and the gate electrode.

5. The semiconductor memory device of claim 1 , wherein the bit line further includes a second conductive line that vertically extends,

wherein the connection part protrudes in the second direction from the second conductive line.

6. The semiconductor memory device of claim 1 , wherein the channel layer includes an amorphous oxide semiconductor or a two-dimensional semiconductor.

7. The semiconductor memory device of claim 1 , wherein a second portion of the channel layer is connected to the data storage element.

8. The semiconductor memory device of claim 1 , wherein the data storage element includes:

a first electrode electrically connected to the channel layer;

a second electrode on the first electrode; and

a dielectric layer between the first electrode and the second electrode.

9. The semiconductor memory device of claim 1 , further comprising:

a peripheral circuit layer between the substrate and the stack structure; and

a through contact that electrically connects at least one of the word line and the bit line to the peripheral circuit layer.

10. A semiconductor memory device, comprising:

a plurality of word lines that are stacked and spaced apart from each other on a substrate, the word lines extending in a first direction parallel to a top surface of the substrate;

a bit line that extends vertically across the word lines;

a gate electrode that protrudes in a second direction from a corresponding one of the word lines, wherein the second direction intersects the first direction and is parallel to the top surface of the substrate;

a channel layer overlapping the gate electrode; and

a data storage element electrically connected to the channel layer,

wherein the channel layer has a hollow shape,

wherein the gate electrode is provided in an internal space of the channel layer, and

wherein the bit line is electrically connected to the channel layer.

11. The semiconductor memory device of claim 10 , wherein

the gate electrode includes a plurality of gate electrodes that protrude in the second direction from the word line, and

the word line has a comb shape.

12. The semiconductor memory device of claim 10 , wherein the channel layer includes an amorphous oxide semiconductor or a two-dimensional semiconductor.

13. The semiconductor memory device of claim 10 , wherein the bit line includes a second conductive line that extends vertically and a connection part that protrudes in the second direction from the second conductive line,

wherein the connection part is electrically connected to the channel layer.

14. The semiconductor memory device of claim 10 , further comprising a peripheral circuit layer electrically connected to the word lines and the bit line,

wherein the peripheral circuit layer is below or above a memory cell array layer.

15. A semiconductor memory device, comprising:

a word line on a substrate, the word line including a first conductive line that extends in a first direction parallel to a top surface of the substrate and a plurality of gate electrodes that protrude in a second direction from the first conductive line, the second direction intersecting the first direction;

a plurality of bit lines that intersect the word line and extend vertically;

a plurality of channel layers, each of the plurality of channel layers disposed between a corresponding one the plurality of bit lines and a corresponding one of the plurality of gate electrodes; and

a plurality of data storage elements, wherein each of the data storage elements is electrically connected to a corresponding one of the channel layers,

wherein the word line has a comb shape, and

wherein a portion of each of the plurality of gate electrodes is disposed inside a corresponding channel layer.

16. The semiconductor memory device of claim 15 , wherein the plurality of channel layers include an amorphous oxide semiconductor or a two-dimensional semiconductor.

17. The semiconductor memory device of claim 15 , wherein each of the plurality of bit lines includes:

a second conductive line that extends vertically; and

a connection part that protrudes in the second direction from the second conductive line,

wherein the connection part is electrically connected to the channel layer that corresponds to the connection part.

18. The semiconductor memory device of claim 15 , wherein each of the plurality of channel layers surrounds a surface of a corresponding gate electrode.

19. The semiconductor memory device of claim 18 , wherein

each of the plurality of channel layers has a hollow shape, and

the corresponding gate electrode is provided in an internal space of the channel layer.