Runtime switchable graphics with a smart multiplexer

1. A computing system comprising:

a first processor having a first graphics display engine;

a second processor having a second graphics display engine; and

a multiplexer to:

receive a first video data stream from the first graphics display engine via a first video data channel;

receive a second video data stream from the second graphics display engine via a second video data channel; and

switch a video output from the first video data stream to the second video data stream based on a switch command to accompany the second video data stream.

2. The computing system of claim 1 , wherein the first graphics display engine is an integrated graphics display engine, wherein the second graphics display engine is a discrete graphics display engine, and wherein to accompany the second video data stream the switch command is embedded in the second video data stream.

3. The computing system of claim 1 , wherein the multiplexer includes a register to store one or more data bits representing the switch command.

4. The computing system of claim 3 , wherein the multiplexer further includes a memory to store information about a display panel connected to an output of the multiplexer.

5. The computing system of claim 4 , wherein the multiplexer is to switch the video output from the first video data stream to the second video data stream while the display panel is in panel self refresh mode.

6. The computing system of claim 1 , further comprising a time base corrector (TBC) to reduce jitter from lack of synchronization between input video data clock signals.

7. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic includes a multiplexer and is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled the one or more substrates to:

receive a first video data stream from a first graphics display engine via a first video data channel;

receive a second video data stream from a second graphics display engine via a second video data channel; and

switch a video output from the first video data stream to the second video data stream based on a switch command to accompany the second video data stream.

8. The semiconductor apparatus of claim 7 , wherein the first graphics display engine is an integrated graphics display engine, wherein the second graphics display engine is a discrete graphics display engine, and wherein to accompany the second video data stream the switch command is embedded in the second video data stream.

9. The semiconductor apparatus of claim 7 , wherein the multiplexer includes a register to store one or more data bits representing the switch command.

10. The semiconductor apparatus of claim 9 , wherein the multiplexer further includes a memory to store information about a display panel connected to an output of the multiplexer.

11. The semiconductor apparatus of claim 10 , wherein the multiplexer is to switch the video output from the first video data stream to the second video data stream while the display panel is in panel self refresh mode.

12. The semiconductor apparatus of claim 7 , wherein the logic is further to implement a time base corrector (TBC) to reduce jitter from lack of synchronization between input video data clock signals.

13. At least one non-transitory computer readable storage medium comprising a set of instructions which, when executed by a computing system, cause the computing system to:

determine a graphics display engine for an application selected for execution;

set display characteristics for the application based on current display characteristics for a different application received from a multiplexer via a video data channel; and

send to the multiplexer, via the video data channel, the display characteristics for the application and a switch command to switch a video output based on the determined graphics display engine, wherein the switch command is to accompany a video data stream output of the determined graphics display engine.

14. The at least one non-transitory computer readable storage medium of claim 13 , wherein the determined graphics display engine is a discrete graphics display engine, and wherein to accompany the video data stream output the switch command is embedded in the video data stream output.

15. The at least one non-transitory computer readable storage medium of claim 13 , wherein the multiplexer includes a register to store one or more data bits representing the switch command.

16. The at least one non-transitory computer readable storage medium of claim 15 , wherein the multiplexer further includes a memory to store information about a display panel connected to an output of the multiplexer.

17. The at least one non-transitory computer readable storage medium of claim 16 , wherein the multiplexer is to switch the video output to the video data stream output of the determined graphics display engine while the display panel is in panel self refresh mode.

18. The at least one non-transitory computer readable storage medium of claim 13 , wherein the computing system includes a time base corrector (TBC) to reduce jitter from lack of synchronization between input video data clock signals.

19. A method comprising:

determining a graphics display engine for an application selected for execution;

setting display characteristics for the application based on current display characteristics for a different application received from a multiplexer via a video data channel; and

sending to the multiplexer, via the video data channel, the display characteristics for the application and a switch command to switch a video output based on the determined graphics engine, wherein the switch command is to accompany a video data stream output of the determined graphics display engine.

20. The method of claim 19 , wherein the determined graphics display engine is a discrete graphics display engine, and wherein to accompany the video data stream output the switch command is embedded in the video data stream output.

21. The method of claim 19 , wherein the multiplexer includes a register to store one or more data bits representing the switch command.

22. The method of claim 21 , wherein the multiplexer further includes a memory to store information about a display panel connected to an output of the multiplexer.

23. The method of claim 22 , wherein the multiplexer is to switch the video output to the video data stream output of the determined graphics display engine while the display panel is in panel self refresh mode.

24. The method of claim 19 , further comprising using a time base corrector (TBC) to reduce jitter from lack of synchronization between video data clock signals.