IP Library › Granted Patent US 12,051,546
Granted Patent B2
US 12,051,546 · App. 17/532,268 · Granted Jul 30, 2024

Multilayer ceramic electronic component

Inventor: Satoshi Muramatsu (Nagaokakyo, JP)
Assignee: MURATA MANUFACTURING CO., LTD.
H01G4/232H01G4/1209H01G4/248H01G4/30
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Quick Facts
Patent No.
US 12,051,546
App. No.
17/532,268
Granted
Jul 30, 2024
Kind
B2
Abstract

A multilayer ceramic capacitor includes a multilayer body including layered ceramic layers and internal electrode layers, and an external electrode on a side surface of the multilayer body and connected to the internal electrode layers. A recess is provided in a surface of the external electrode on one side of opposing main surfaces of the multilayer ceramic capacitor.

Claims (36)

1. A multilayer ceramic electronic component comprising:

a multilayer body including a plurality of layered ceramic layers and a plurality of internal electrode layers, the multilayer body including a first main surface and a second main surface opposed to each other in a height direction, a first side surface and a second side surface opposed to each other in a width direction orthogonal or substantially orthogonal to the height direction, and a third side surface and a fourth side surface opposed to each other in a length direction orthogonal or substantially orthogonal to the height direction and the width direction; and

a plurality of external electrodes on the first, second, third, and fourth side surfaces of the multilayer body; wherein

the plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers, the plurality of first internal electrode layers and the plurality of second internal electrode layers being alternately layered with the ceramic layers being interposed therebetween;

each of the plurality of first internal electrode layers includes a first drawn portion extending to at least one of the first side surface, the second side surface, the third side surface, and the fourth side surface and a second drawn portion extending to at least one side surface other than the side surface to which the first drawn portion extends;

each of the second internal electrode layers includes a third drawn portion extending to at least one of the first side surface, the second side surface, the third side surface, and the fourth side surface and a fourth drawn portion extending to at least one side surface other than the side surface to which the third drawn portion extends;

the plurality of external electrodes include:

a first external electrode connected to the first drawn portion and covering a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the third side surface;

a second external electrode connected to the second drawn portion and covering a portion of the first main surface, a portion of the second main surface, a portion of the second side surface, and a portion of the fourth side surface;

a third external electrode connected to the third drawn portion and covering a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the fourth side surface; and

a fourth external electrode connected to the fourth drawn portion and covering a portion of the first main surface, a portion of the second main surface, a portion of the second side surface, and a portion of the third side surface;

a recess is provided in a surface of at least two external electrodes of the first external electrode to the fourth external electrode on one of the first main surface and the second main surface; and

a maximum dimension of the recess in each of the width direction and the length direction is less than a maximum dimension of the at least two external electrodes in each of the width direction and the length direction.

2. The multilayer ceramic electronic component according to claim 1 , wherein the first external electrode, the second external electrode, the third external electrode, and the fourth external electrode each include an underlying electrode layer, a first plated layer on the underlying electrode layer and on the first side surface, the second side surface, the third side surface, and the fourth side surface, a second plated layer on the first plated layer, and a third plated layer on the second plated layer.

3. The multilayer ceramic electronic component according to claim 1 , wherein the recess has a size not less than about 1.1% and not greater than about 34.9% of an area of the external electrode on the first main surface or the second main surface at which the recess is provided.

4. The multilayer ceramic electronic component according to claim 2 , wherein the recess has a depth not less than about 2.5% and not greater than about 40% of a thickness of the third plated layer.

5. The multilayer ceramic electronic component according to claim 2 , wherein

the underlying electrode layer defines and functions as a thin electrode including at least one of Ni, Cr, Cu, or Ti;

the first plated layer is a Cu plated layer;

the second plated layer is a Ni plated layer; and

the third plated layer is a Sn plated layer.

6. The multilayer ceramic electronic component according to claim 1 , wherein a number of the plurality of ceramic layers is at least ten and at most seven hundred.

7. The multilayer ceramic electronic component according to claim 1 , wherein a dimension of the multilayer body in the length direction of not less than about 0.43 mm and not greater than about 0.73 mm.

8. The multilayer ceramic electronic component according to claim 1 , wherein a relationship between a dimension of the multilayer body in the width directions and a dimension of the multilayer body in the length direction satisfies about 0.85≤w/l≤about 1.0.

9. The multilayer ceramic electronic component according to claim 1 , wherein a dimension of the multilayer body in the height direction is not less than about 50 μm and not greater than about 90 μm.

10. The multilayer ceramic electronic component according to claim 1 , wherein each of the plurality of ceramic layers includes BaTiO 3 , CaTiO 3 , SrTiO 3 , or CaZrO 3 as a main component.

11. The multilayer ceramic electronic component according to claim 10 , wherein each of the plurality of ceramic layers further includes an Mn compound, an Fe compound, a Cr compound, a Co compound, or an Ni compound as a sub-component.

12. The multilayer ceramic electronic component according to claim 1 , wherein an average thickness of the plurality of ceramic layers is not less than about 0.4 μm and not greater than about 5 μm.

13. The multilayer ceramic electronic component according to claim 1 , wherein each of the plurality of internal electrode layers includes Ni, Cu, Ag, Pd, or Au, or an alloy including at least one of Ni, Cu, Ag, Pd, or Au.

14. The multilayer ceramic electronic component according to claim 1 , wherein an average thickness of each of the plurality of internal electrode layers is not less than about 0.2 μm and not greater than about 2.0 μm.

15. The multilayer ceramic electronic component according to claim 1 , wherein a diameter of the recess is not less than about 20 μm and not greater than about 150 μm.

16. The multilayer ceramic electronic component according to claim 2 , wherein a thickness of the underlying electrode layer is not less than about 50 nm and not greater than about 400 nm.

17. The multilayer ceramic electronic component according to claim 2 , wherein a thickness of the underlying electrode layer is not less than about 50 nm and not greater than about 130 nm.

18. The multilayer ceramic electronic component according to claim 2 , wherein a thickness of the first plated layer is not less than about 2 μm and not greater than about 8 μm.

19. The multilayer ceramic electronic component according to claim 2 , wherein a thickness of the second plated layer is not less than about 2 μm and not greater than about 4 μm.

20. The multilayer ceramic electronic component according to claim 2 , wherein a thickness of the third plated layer is not less than about 2 μm and not greater than about 4 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 22, 2021
From: MURAMATSU, SATOSHI
To: MURATA MANUFACTURING CO., LTD.
Reel/Frame 058182/0051 →
Priority Claims (1)
JP 2020-214913 · Dec 24, 2020 · national
Continuity (1)
Related Publication 20220208459A1 · Jun 30, 2022