PN-body-tied field effect transistors
Disclosed herein are PN-body-tied field effect transistors (PNBTFETs), as well as related devices and methods. In some embodiments, an integrated circuit (IC) structure may include: a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type; a gate that at least partially wraps around the channel region; and a conductive contact in contact with the contact region.
1. An integrated circuit (IC) structure, comprising:
a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type;
a gate that at least partially wraps around the channel region; and
a conductive contact in contact with the contact region,
wherein sidewalls of the intermediate region are in contact with an insulator material, sidewalls of the conductive contact are in contact with the insulator material, and sidewalls of the contact region are in contact with the insulator material.
2. The IC structure of claim 1 , wherein the channel region is in a top portion of the fin, and the contact region is in a bottom portion of the fin.
3. The IC structure of claim 1 , wherein the first type is a p-type and the second type is an n-type, or the first type is an n-type and the second type is a p-type.
4. The IC structure of claim 1 , wherein a dopant level in the contact region is greater than a dopant level in the channel region.
5. The IC structure of claim 1 , wherein a dopant level in the contact region is greater than a dopant level in the channel region by at least two orders of magnitude.
6. The IC structure of claim 1 , further comprising:
source or regions adjacent to the channel region, wherein the source or drain regions include a dopant of the second type.
7. The IC structure of claim 1 , wherein the insulator material in contact with the sidewalls of the intermediate region is materially continuous with the insulator material in contact with the sidewalls of the contact region.
8. The IC structure of claim 1 , wherein the insulator material in contact with the sidewalls of the intermediate region is materially continuous with the insulator material in contact with the sidewalls of the contact region and with the insulator material in contact with the sidewalls of the conductive contact.
9. The IC structure of claim 1 , wherein the channel region is in contact with the intermediate region.
10. The IC structure of claim 1 , wherein the intermediate region is in direct physical contact with either the contact region or the channel region.
11. An integrated circuit (IC) structure, comprising:
a first fin including a first channel region, a first contact region, and a first intermediate region between the first contact region and the first channel region, wherein the first channel region includes a dopant of a first type, the first intermediate region includes a dopant of a second type different from the first type, and the first contact region includes a dopant of the first type;
a first conductive contact in contact with the first contact region;
a second fin including a second channel region, a second contact region, and a second intermediate region between the second contact region and the second channel region, wherein the second channel region includes a dopant of the first type, the second intermediate region includes a dopant of the second type, and the second contact region includes a dopant of the first type;
a second conductive contact in contact with the second contact region;
a gate that at least partially wraps around the first channel region; and
an insulator material extending between, and being in contact with, the first intermediate region and the second intermediate region.
12. The IC structure of claim 11 , wherein the gate further at least partially wraps around the second channel region.
13. The IC structure of claim 11 , wherein:
the first intermediate region has a sidewall facing the second intermediate region,
the second intermediate region has a sidewall facing the first intermediate region, and
the insulator material fills a volume defined by the sidewall of the first intermediate region and the sidewall of the second intermediate region.
14. The IC structure of claim 11 , wherein the insulator material is further extending between, and is in contact with, the first contact region and the second contact region.
15. The IC structure of claim 14 , wherein the insulator material is further extending between, and is in contact with, the first conductive contact and the second conductive contact.
16. The IC structure of claim 11 , wherein the insulator material is a part of an insulator structure, and wherein the insulator structure is a materially continuous structure of the insulator material having portions in contact with the first contact region, the second contact region, the first conductive contact, and the second conductive contact.
17. An integrated circuit (IC) structure, comprising: a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the intermediate region is in direct physical contact with the contact region, the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type; a gate that at least partially wraps around the channel region; and a conductive contact in contact with the contact region, wherein no gate wraps around sidewalls of the intermediate region.
18. The IC structure of claim 17 , wherein sidewalls of the intermediate region and sidewalls of the contact region are in contact with an insulator material.
19. The IC structure of claim 17 , wherein sidewalls of the intermediate region are in contact with an insulator material, sidewalls of the conductive contact are in contact with the insulator material, and sidewalls of the contact region are in contact with the insulator material.
20. The IC structure of claim 17 , wherein sidewalls of the intermediate region are in contact with an insulator material, sidewalls of the contact region are in contact with the insulator material, and the insulator material in contact with the sidewalls of the intermediate region is materially continuous with the insulator material in contact with the sidewalls of the contact region.
21. A computing device, comprising:
a circuit board; and
an integrated circuit (IC) package coupled to the circuit board, wherein:
the IC package includes an IC die,
the IC die includes:
a fin including a channel region, a contact region, and an intermediate region between the contact region and the channel region, wherein the channel region includes a dopant of a first type, the intermediate region includes a dopant of a second type different from the first type, and the contact region includes a dopant of the first type,
a gate that at least partially wraps around the channel region, and
a conductive contact in contact with the contact region,
wherein sidewalls of the intermediate region are in contact with an insulator material, sidewalls of the conductive contact are in contact with the insulator material, and sidewalls of the contact region are in contact with the insulator material.
22. The computing device of claim 21 , further comprising:
wireless communication circuitry electrically coupled to the circuit board.
23. The computing device of claim 21 , wherein the computing device is a tablet computing device, a handheld computing device, a smart phone, a wearable computing device, or a server.