IP Library › Granted Patent US 12,051,726
Granted Patent B2
US 12,051,726 · App. 17/550,646 · Granted Jul 30, 2024

Semiconductor device and memory device

Inventors: Shunpei Yamazaki (Tokyo, JP); Daisuke Yamaguchi (Kanagawa, JP); Shinobu Kawaguchi (Kanagawa, JP); Yoshihiro Komatsu (Kanagawa, JP); Toshikazu Ohno (Kanagawa, JP); Yasumasa Yamane (Kanagawa, JP); Tomosato Kanagawa (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L29/26H10B12/0335H10B12/05H10B12/31
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Quick Facts
Patent No.
US 12,051,726
App. No.
17/550,646
Granted
Jul 30, 2024
Kind
B2
Abstract

A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes an oxide semiconductor, a first insulator in contact with the oxide semiconductor, and a second insulator in contact with the first insulator. The first insulator includes excess oxygen. The second insulator has a function of trapping or fixing hydrogen. Hydrogen in the oxide semiconductor is bonded to the excess oxygen. The hydrogen bonded to the excess oxygen passes through the first insulator and is trapped or fixed in the second insulator. The excess oxygen bonded to the hydrogen remains in the first insulator as the excess oxygen.

Claims (27)

1. A semiconductor device comprising:

a source electrode and a drain electrode of a transistor over a first insulator;

an oxide semiconductor of the transistor over the first insulator;

a gate insulator over the oxide semiconductor and between the source electrode and the drain electrode;

a gate electrode over the gate insulator and between the source electrode and the drain electrode;

a second insulator over the source electrode and the drain electrode and comprising an opening between the source electrode and the drain electrode;

a third insulator over and in contact with the second insulator;

a fourth insulator over and in contact with the third insulator;

a fifth insulator over and in contact with the fourth insulator;

a first wiring electrically connected to one of the source electrode and the drain electrode; and

a second wiring electrically connected to the other of the source electrode and the drain electrode,

wherein the oxide semiconductor is positioned inside the opening of the second insulator,

wherein the fourth insulator overlaps with the oxide semiconductor, the gate insulator, and the gate electrode,

wherein the first insulator and the fourth insulator are in contact with each other in each of a first region and a second region where the second insulator and the third insulator do not exist,

wherein the fourth insulator and the fifth insulator are in contact with each other in each of the first region and the second region, and

wherein the first wiring comprises a region overlapping with the first region with a sixth insulator interposed therebetween, and wherein the second wiring comprise a region overlapping with the second region with the sixth insulator interposed therebetween.

2. The semiconductor device according to claim 1 ,

wherein the second insulator comprises excess oxygen,

wherein the third insulator is configured to trap or fix hydrogen, and

wherein the fourth insulator has a barrier property against hydrogen.

3. The semiconductor device according to claim 1 ,

wherein the oxide semiconductor comprises indium, gallium, and zinc.

4. The semiconductor device according to claim 1 ,

wherein the second insulator comprises silicon oxynitride, and

wherein the third insulator comprises aluminum oxide.

5. The semiconductor device according to claim 1 ,

wherein the fourth insulator comprises silicon nitride.

Priority Claims (2)
JP 2018-248150 · Dec 28, 2018 · national
JP 2019-011158 · Jan 25, 2019 · national
Continuity (2)
Continuation 16693974 · Nov 25, 2019
Related Publication 20220102505A1 · Mar 31, 2022