Memory array gate structures

1. A method comprising:

forming a first conductive line and a second conductive line over a semiconductor substrate, wherein the second conductive line is disposed over the first conductive line and is insulated from the first conductive line;

patterning a first trench extending through the first conductive line and the second conductive line;

depositing a ferroelectric (FE) material along sidewalls and a bottom surface of the first trench, the FE material comprising a hafnium-comprising compound, and the hafnium-comprising compound comprising a rare earth metal;

depositing an oxide semiconductor (OS) layer over the FE material, the OS layer extending along the sidewalls and the bottom surface of the first trench;

forming a first dielectric material over and contacting the OS layer; and

forming a third conductive line and a fourth conductive line extending through the first dielectric material.

2. The method of claim 1 , wherein the FE material comprises hafnium zirconium oxide (HfZnO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium gadolinium oxide (HfGdO), hafnium silicon oxide (HfSiO), hafnium zirconium lanthanum oxide (HfZrLaO), hafnium zirconium gadolinium oxide (HfZrGdO), hafnium zirconium yttrium oxide (HfZrYO), hafnium zirconium cerium oxide (HfZrCeO), hafnium zirconium strontium oxide (HfZrSrO).

3. The method of claim 1 , wherein depositing the FE material comprises an atomic layer deposition process, and wherein the atomic layer deposition (ALD) process comprises an annealing process that is performed at a temperature of 400° C. or less.

4. The method of claim 3 , wherein the ALD process comprises:

forming a first monolayer of hafnium oxide;

forming a second monolayer of zirconium oxide contacting the first monolayer; and

forming a third monolayer of a rare earth metal oxide contacting the second monolayer.

5. The method of claim 3 , wherein the ALD process comprises:

forming a first monolayer of hafnium oxide;

forming a second monolayer of a rare earth metal oxide contacting the first monolayer; and

forming a third monolayer of zirconium oxide contacting the second monolayer.

6. The method of claim 3 , wherein the ALD process comprises:

forming a first monolayer of a rare earth metal oxide;

forming a second monolayer of hafnium oxide contacting the first monolayer; and

forming a third monolayer of zirconium oxide contacting the second monolayer.

7. The method of claim 3 , wherein the ALD process comprises:

forming a plurality of first monolayers of hafnium oxide;

forming a plurality of second monolayers of zirconium oxide contacting the plurality of first monolayers; and

forming a plurality of third monolayers of molybdenum oxide contacting the plurality of second monolayers.

8. A method comprising:

forming a first memory cell and a second memory cell over a semiconductor substrate, the second memory cell being disposed over the first memory cell, forming the first memory cell and the second memory cell comprising:

depositing a ferroelectric material on a sidewall of a first word line, and the ferroelectric material comprising a rare earth metal;

depositing an oxide semiconductor material on a sidewall of the ferroelectric material;

depositing a dielectric material on a sidewall of the oxide semiconductor material;

patterning a first opening and a second opening extending through the dielectric material; and

forming a source line in the first opening and a bit line in the second opening, the source line being insulated from the bit line by the dielectric material.

9. The method of claim 8 , wherein the ferroelectric material further comprises Hf, Zr, or a combination thereof.

10. The method of claim 8 , depositing the ferroelectric material comprises an atomic layer deposition process comprising:

depositing a plurality of monolayers; and

annealing the plurality of monolayers to form an orthorhombic phase crystalline structure.

11. The method of claim 10 , wherein annealing the plurality of monolayers is performed at a temperature less than 400° C.

12. The method of claim 8 , wherein the oxide semiconductor material comprises ZnO, InWO, InGaZnO, InZnO, ITO, or a combination thereof.

13. The method of claim 8 , wherein the rare earth metal is La, Y, Gd, Ce, or Sr.

14. The method of claim 8 , wherein the ferroelectric material is further deposited on a sidewall of a second word line over and electrically isolated from the first word line.

15. A method comprising:

patterning a first trench extending through a first conductive line;

depositing a ferroelectric (FE) material along sidewalls and a bottom surface of the first trench, wherein depositing the FE material comprises an atomic layer deposition (ALD) process to deposit a hafnium-comprising compound, and wherein the hafnium-comprising compound further comprises a rare earth metal; and

depositing an oxide semiconductor (OS) layer over the FE material, the OS layer extending along the sidewalls and the bottom surface of the first trench.

16. The method of claim 15 , wherein the ALD process comprises:

forming a first monolayer of hafnium oxide; and

forming a second monolayer of a rare earth metal oxide over the first monolayer.

17. The method of claim 16 , wherein the ALD process further comprises:

forming a third monolayer of zirconium oxide between the first monolayer and the second monolayer.

18. The method of claim 16 , wherein the ALD process further comprises:

forming a third monolayer of zirconium oxide over the second monolayer.

19. The method of claim 18 , wherein the ALD process further comprises

forming a fourth monolayer of hafnium oxide contacting the first monolayer; and

forming a fifth monolayer of a rare earth metal oxide directly contacting the second monolayer.

20. The method of claim 15 further comprising after depositing the FE material, performing an annealing process on the FE material at a temperature of 400° C. or less, wherein the FE material has an orthorhombic lattice structure as a result of the annealing process.