Power management circuit operable with group delay

1. A voltage processing circuit comprising:

a first group delay circuit configured to receive a time-variant target voltage and generate a first time-variant target voltage having a first group delay relative to the time-variant target voltage;

a second group delay circuit configured to receive the time-variant target voltage and generate a second time-variant target voltage having a second group delay relative to the time-variant target voltage; and

a target voltage generation circuit configured to:

receive the first time-variant target voltage and the second time-variant target voltage; and

generate a windowed time-variant target voltage higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a plurality of group delay tolerance windows each defined by the first group delay and the second group delay.

2. The voltage processing circuit of claim 1 , wherein each of the first group delay and the second group delay is one of a positive group delay and a negative group delay.

3. The voltage processing circuit of claim 1 , further comprising a control circuit configured to:

receive a determined group delay; and

determine at least the first group delay and the second group delay based on the determined group delay.

4. The voltage processing circuit of claim 1 , further comprising at least one third group delay circuit configured to generate at least one third time-variant target voltage having at least one third group delay relative to the time-variant target voltage, wherein the target voltage generation circuit is further configured to generate the windowed time-variant target voltage higher than or equal to a highest one of the first time-variant target voltage, the second time-variant target voltage, and the at least one third time-variant target voltage in the plurality of group delay tolerance windows.

5. The voltage processing circuit of claim 4 wherein the at least one third group delay is equal to an average of the first group delay and the second group delay.

6. The voltage processing circuit of claim 4 , wherein the first group delay circuit, the second group delay circuit, and the at least one third group delay circuit each comprises a respective group delay circuit configured to generate a respective one of the first time-variant target voltage, the second time-variant target voltage, and the at least one third time-variant target voltage having a respective one of the first group delay, the second group delay, and the at least one third group delay relative to the time-variant target voltage.

7. The voltage processing circuit of claim 6 , wherein the respective group delay circuit in any of the first group delay circuit, the second group delay circuit, and the at least one third group delay circuit comprises a negative group delay circuit configured to generate a respective one of the first time-variant target voltage, the second time-variant target voltage, and the at least one third time-variant target voltage having a negative group delay relative to the time-variant target voltage.

8. The voltage processing circuit of claim 7 , wherein the negative group delay circuit comprises an inverted negative group delay circuit.

9. The voltage processing circuit of claim 6 , wherein the respective group delay circuit in any of the first group delay circuit, the second group delay circuit, and the at least one third group delay circuit comprises a positive group delay circuit configured to generate a respective one of the first time-variant target voltage, the second time-variant target voltage, and the at least one third time-variant target voltage having a positive group delay relative to the time-variant target voltage.

10. The voltage processing circuit of claim 9 , wherein the positive group delay circuit is coupled to a pre-emphasis circuit configured to keep the positive group delay constant in the respective one of the first time-variant target voltage, the second time-variant target voltage, and the at least one third time-variant target voltage having the positive group delay relative to the time-variant target voltage.

11. The voltage processing circuit of claim 6 , wherein the first group delay circuit, the second group delay circuit, and the at least one third group delay circuit each comprises a respective nonlinear amplifier configured to introduce a nonlinear gain in a respective one of the first time-variant target voltage, the second time-variant target voltage, and the at least one third time-variant target voltage.

12. The voltage processing circuit of claim 1 , further comprising an offset circuit configured to apply a direct current (DC) voltage to the windowed time-variant target voltage.

13. The voltage processing circuit of claim 1 , further comprising a target voltage amplifier configured to amplify the windowed time-variant target voltage.

14. A power management circuit comprising:

a target voltage circuit comprising:

a voltage processing circuit comprising:

a first group delay circuit configured to receive a time-variant target voltage and generate a first time-variant target voltage having a first group delay relative to the time-variant target voltage;

a second group delay circuit configured to receive the time-variant target voltage and generate a second time-variant target voltage having a second group delay relative to the time-variant target voltage; and

a target voltage generation circuit configured to:

receive the first time-variant target voltage and the second time-variant target voltage; and

generate a windowed time-variant target voltage higher than or equal to a highest one of the first time-variant target voltage and the second time-variant target voltage in a plurality of group delay tolerance windows each defined by the first group delay and the second group delay; and

an envelope tracking integrated circuit (ETIC) configured to generate a time-variant voltage based on the windowed time-variant target voltage.

15. The power management circuit of claim 14 , wherein the target voltage circuit further comprises:

an envelope detector circuit configured to detect a time-variant envelope of an analog signal; and

an analog look-up table (LUT) circuit configured to generate the time-variant target voltage based on the detected time-variant envelope of the analog signal.

16. The power management circuit of claim 14 , wherein the first group delay circuit and the second group delay circuit are each configured to receive the time-variant target voltage from a transceiver circuit coupled externally to the power management circuit.

17. The power management circuit of claim 14 , wherein each of the first group delay and the second group delay is one of a positive group delay and a negative group delay.

18. The power management circuit of claim 14 , wherein the voltage processing circuit further comprises a control circuit configured to:

receive a determined group delay; and

determine at least the first group delay and the second group delay based on the determined group delay.

19. The power management circuit of claim 18 , wherein the control circuit is further configured to receive the determined group delay from a transceiver circuit coupled externally to the power management circuit.

20. The power management circuit of claim 18 , further comprising a delay detector circuit configured to determine the determined group delay.