In-system validation of interconnects by error injection and measurement
Systems and devices can include an error injection register comprising error injection parameter information. The systems and devices can also include error injection logic circuit to read error injection parameter information from the error injection register, and inject an error into a flow control unit (Flit); and protocol stack circuitry to transmit the Flit comprising the error on a multilane link. The injected error can be detected by a receiver and used to test and characterize various aspects of a link, such as bit error rate, error correcting code, cyclic redundancy check, replay capabilities, error logging, and other characteristics of the link.
1. An apparatus comprising:
an error injection configuration register comprising error injection parameter information, the error injection parameter information comprising an indication of a spacing, in terms of a number of flow control units (Flits), between occurrences of injected errors; and
an error injection logic circuit to:
read the error injection parameter information from the error injection configuration register, and
inject an error into a flow control unit (Flit) based on the error injection parameter information; and
protocol stack circuitry to transmit the Flit comprising the error on a multilane link.
2. The apparatus of claim 1 , wherein the error injection parameter information comprises information to activate or deactivate the error injection logic circuit.
3. The apparatus of claim 1 , wherein:
the error injection parameter information comprises an indication of a number of errors to be injected into the Flit; and
the error injection logic circuit is to inject the number of errors into the Flit based on the indication of the number of errors to be injected in the error injection parameter information.
4. The apparatus of claim 1 , wherein:
the error injection parameter information comprises an indication of a Flit type that the error is to be injected into; and
the error injection logic circuit is to inject an error into a Flit based on the Flit type.
5. The apparatus of claim 4 , wherein the indication of a Flit type in the error injection parameter information comprises an indication that an error is to be injected into any non-Idle Flit, a Payload Flit, a No Operation (NOP) Flit, or any type of Flit.
6. The apparatus of claim 1 , wherein:
the error injection parameter information comprises an indication of a type of error to be injected into the Flit; and
the error injection logic circuit is to inject the type of errors into the Flit based on the indication of the type of errors to be injected in the error injection parameter information.
7. The apparatus of claim 6 , wherein the indication of the type of error can indicate that the error can be a correctable error or an uncorrectable error.
8. The apparatus of claim 7 , wherein the indication of the type of error can indicate that the error is to be a correctable error in one forward error correction group or a correctable error in three forward error correction groups.
9. The apparatus of claim 7 , wherein the indication of the type of error can indicate the error is to be randomly selected between a correctable error or an uncorrectable error.
10. The apparatus of claim 1 , wherein:
the error injection parameter information comprises an indication of a magnitude of an error to be injected into the Flit; and
the error injection logic circuit is to inject the error with the magnitude into the Flit based on the indication of the magnitude of errors to be injected in the error injection parameter information.
11. The apparatus of claim 1 , further comprising a port to receive a Flit;
wherein:
the error injection parameter information comprises an indication to inject a negative acknowledgment (NAK) into a received Flit; and
the error injection logic circuit is to inject a NAK into a received Flit.
12. The apparatus of claim 1 , further comprising a port to receive a Flit;
wherein:
the error injection parameter information comprises an indication to force a replay of the received Flit; and
the protocol stack circuitry to cause the Flit to be retransmitted.
13. The apparatus of claim 1 , further comprising:
an ordered set error register comprising ordered set error injection parameter information;
an ordered set error injection circuit to:
determine that ordered set error injection is activated,
read the ordered set error injection parameter information, and
inject an error into an ordered set; and
the protocol stack circuitry to transmit the ordered set with the error on a multilane link.
14. A method comprising:
encoding, by protocol stack circuitry, a flow control unit (Flit);
encoding, by error injection circuitry, an error into the Flit based on an error injection parameter stored in an error injection register, the error injection parameter indicating a spacing, in terms of a number of Flits, between occurrences of injected errors;
transmitting the Flit on a multilane link with the error.
15. The method of claim 14 , further comprising:
calculating error correcting code for the Flit prior to encoding the error into the Flit; and
encoding the Flit with error correcting code prior to encoding the error into the Flit.
16. The method of claim 14 , further comprising:
calculating cyclic redundancy check code for the Flit prior to encoding the error into the Flit; and
encoding the Flit with cyclic redundancy check code for the Flit prior to encoding the error into the Flit.
17. The method of claim 14 , further comprising:
determining an additional error injection parameter from the error injection register;
encoding the error into the Flit based on the additional error injection parameter.
18. The method of claim 14 , wherein the error injection parameter comprises one or more of an error magnitude, a number of errors, a Flit type, a type of error being encoded, or an error offset.
19. The method of claim 14 , further comprising:
receiving a negative acknowledgment message for a previously transmitted Flit; and
replaying the previously transmitted Flit.
20. A system comprising:
a host device comprising a transmitter to transmit a flow control unit (Flit) over a multilane link, the host device comprising:
error injection register comprising error injection parameter information, the error injection parameter information comprising an indication of a spacing, in terms of a number of flow control units (Flits), between occurrences of injected errors; and
error injection logic circuit to:
read error injection parameter information from the error injection register, and
inject an error into a Flit based on the error injection parameter information; and
protocol stack circuitry to transmit the Flit comprising the error on a multilane link;
an endpoint device comprising a receiver port to receive the Flit, the receiver port comprising:
error detection circuitry to detect the error in a Flit, and
an error log to store information pertaining to the error in the Flit.
21. The system of claim 20 , further comprising protocol stack circuitry to:
calculate error correcting code for the Flit prior to encoding the error into the Flit; and
encode the Flit with error correcting code prior to encoding the error into the Flit.
22. The system of claim 20 , further comprising protocol stack circuitry to:
calculate cyclic redundancy check code for the Flit prior to encoding the error into the Flit; and
encode the Flit with cyclic redundancy check code for the Flit prior to encoding the error into the Flit.
23. The system of claim 20 , the error injection circuitry to:
determine an error injection parameter from an error injection parameter register;
encode the error into the Flit based on the error injection parameter.
24. The system of claim 23 , wherein the error injection parameter comprises one or more of an error magnitude, a number of errors, a Flit type, a type of error being encoded, or an error offset.