Semiconductor devices

1. A semiconductor device, comprising:

a capacitor,

wherein the capacitor comprises a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction perpendicular to an interface between each of the bottom electrodes and the dielectric layer,

wherein the dielectric layer is interposed between the bottom electrode and the top electrode and comprises a first dielectric layer and a second dielectric layer that are stacked in the first direction,

the first dielectric layer is anti-ferroelectric,

the second dielectric layer is ferroelectric, and

a thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.

2. The semiconductor device of claim 1 , wherein a difference between the thermal expansion coefficient of the first dielectric layer and the thermal expansion coefficient of the second dielectric layer is greater than or equal to 3.0×10 −6 /K.

3. The semiconductor device of claim 1 , wherein the first dielectric layer comprises an anti-ferroelectric first crystal phase, and

the first crystal phase is at least one of a tetragonal phase, an orthorhmobic phase, or a rhombohedral phase.

4. The semiconductor device of claim 3 , wherein the second dielectric layer comprises a ferroelectric second crystal phase, and

the second crystal phase is at least one of a tetragonal phase, an orthorhmobic phase, or a rhombohedral phase.

5. The semiconductor device of claim 4 , wherein the first dielectric layer further comprises a paraelectric sub-crystal phase,

the sub-crystal phase is a monoclinic phase, and

in the first dielectric layer, a fraction of the first crystal phase is greater than a fraction of the sub-crystal phase.

6. The semiconductor device of claim 4 , wherein the second dielectric layer further comprises a paraelectric sub-crystal phase,

the sub-crystal phase is a monoclinic phase, and

in the second dielectric layer, a fraction of the second crystal phase is greater than a fraction of the sub-crystal phase.

7. The semiconductor device of claim 4 , wherein, in the dielectric layer, a fraction of the first crystal phase is greater than a fraction of the second crystal phase.

8. The semiconductor device of claim 7 , wherein at least one of the first and second dielectric layers further comprises a paraelectric sub-crystal phase,

the sub-crystal phase is a monoclinic phase, and

in the dielectric layer, a fraction of the sub-crystal phase is less than the fraction of the first crystal phase and the fraction of the second crystal phase.

9. The semiconductor device of claim 1 , wherein each of the first and second dielectric layers has a thickness in the first direction, and

the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

10. The semiconductor device of claim 1 , wherein

a plurality of the first dielectric layers are provided,

a plurality of the second dielectric layers are provided, and

the dielectric layer comprises the plurality of first dielectric layers and the plurality of second dielectric layers that are alternately stacked in the first direction between the bottom electrode and the top electrode.

11. The semiconductor device of claim 10 , wherein each of the dielectric layer, the first dielectric layers and the second dielectric layers has a thickness in the first direction, and

a ratio of a sum of the thicknesses of the first dielectric layers to a total thickness of the dielectric layer is greater than a ratio of a sum of the thicknesses of the second dielectric layers to the total thickness of the dielectric layer.

12. A semiconductor device, comprising:

a substrate;

a plurality of bottom electrodes disposed on the substrate and that are horizontally spaced apart from each other;

a top electrode that covers the bottom electrodes; and

a dielectric layer interposed between each of the bottom electrodes and the top electrode,

wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer that are stacked in a third direction perpendicular to an interface between each of the bottom electrodes and the dielectric layer,

the first dielectric layer is anti-ferroelectric,

the second dielectric layer is ferroelectric, and

a thermal expansion coefficient of the first dielectric layer is greater than a thermal expansion coefficient of the second dielectric layer.

13. The semiconductor device of claim 12 , wherein a difference between the thermal expansion coefficient of the first dielectric layer and the thermal expansion coefficient of the second dielectric layer is greater than or equal to 3.0×10 −6 /K and is less than or equal to 10.0×10 −6 /K.

14. The semiconductor device of claim 12 , wherein

the first dielectric layer comprises an anti-ferroelectric first crystal phase,

the second dielectric layer comprises a ferroelectric second crystal phase, and

in the dielectric layer, a fraction of the first crystal phase is greater than a fraction of the second crystal phase.

15. The semiconductor device of claim 14 , wherein at least one of the first and second dielectric layers further comprises a paraelectric sub-crystal phase, and

in the dielectric layer, a fraction of the sub-crystal phase is less than the fraction of the first crystal phase and the fraction of the second crystal phase.

16. The semiconductor device of claim 12 , wherein each of the first and second dielectric layers has a thickness in the third direction, and

the thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

17. The semiconductor device of claim 12 , wherein each of the bottom electrodes has one of a pillar shape, a cup shape, or a semi-pillar shape.

18. The semiconductor device of claim 12 , further comprising:

a plurality of bit lines disposed on the substrate, wherein the plurality of bit lines extend in a first direction and are spaced apart from each other in a second direction, wherein the first and second directions are parallel to a bottom surface of the substrate and cross each other; and

a plurality of storage node contacts interposed between the bit lines and spaced apart from each other in the first direction,

wherein each of the bottom electrodes is electrically connected to a corresponding storage node contact.

19. The semiconductor device of claim 18 , wherein the substrate comprises active patterns,

each of the active patterns comprises a first impurity injection region and second impurity injection regions that are spaced apart from each other with the first impurity injection region interposed therebetween,

each of the bit lines is electrically connected to the first impurity injection region, and

each of the storage node contacts is electrically connected to a corresponding second impurity injection region.

20. A semiconductor device, comprising:

a capacitor,

wherein the capacitor comprises a bottom electrode, a dielectric layer, and a top electrode that are sequentially stacked in a first direction pependicular to an interface between each of the bottom electrodes and the dielectric layer,

wherein the dielectric layer is interposed between the bottom electrode and the top electrode and comprises a first dielectric layer and a second dielectric layer that are stacked in the first direction,

the first dielectric layer comprises an anti-ferroelectric first crystal phase,

the second dielectric layer comprises a ferroelectric second crystal phase,

at least one of the first and second dielectric layers further comprises a paraelectric sub-crystal phase,

in the dielectric layer, a fraction of the sub-crystal phase is less than a fraction of the first crystal phase and a fraction of the second crystal phase.