Memory chip structure having GAA transistors with different threshold voltages and work functions for improving performances in multiple applications

1. A semiconductor memory chip, comprising:

a first memory cell comprising:

a first pull-up transistor including a first gate stack having a first gate dielectric layer wrapping around each of a first plurality of nanostructures,

a first pull-down transistor including a second gate stack having a second gate dielectric layer wrapping around each of a second plurality of nanostructures; and

a second memory cell comprising:

a second pull-up transistor including a third gate stack having a third gate dielectric layer wrapping around each of a third plurality of nanostructures,

a second pull-down transistor including a fourth gate stack having a fourth gate dielectric layer wrapping around each of a fourth plurality of nanostructures,

wherein the first gate dielectric layer is free of lanthanum and the second gate dielectric layer is doped with lanthanum such that the first memory cell operates at a first threshold voltage,

wherein the third gate dielectric layer is doped with lanthanum and the fourth gate dielectric layer is free of lanthanum such that the second memory cell operates at a second threshold voltage, and the second threshold voltage is greater than the first threshold voltage.

2. The semiconductor memory chip of claim 1 ,

wherein the first pull-up transistor and the second pull-up transistor are of p-type conductivity,

wherein the first pull-down transistor and the second pull-down transistor are of n-type conductivity.

3. The semiconductor memory chip of claim 1 ,

wherein the first memory cell further comprises a first pass-gate transistor having a fifth gate dielectric layer wrapping around each of a fifth plurality of nanostructures,

wherein the second memory cell further comprises a second pass-gate transistor having a sixth gate dielectric layer wrapping around each of a sixth plurality of nanostructures,

wherein the fifth gate dielectric layer is doped with lanthanum and the sixth gate dielectric layer is free of lanthanum, and the first pass-gate transistor and the second pass-gate transistor are of n-type conductivity.

4. The semiconductor memory chip of claim 1 , wherein the first memory cell and the second memory cell have a same cell length along a first direction and a same cell width along a second direction perpendicular to the first direction.

5. The semiconductor memory chip of claim 1 , wherein the second memory cell is connected to a write-assist circuit while the first memory cell is not connected to a write-assist circuit.

6. The semiconductor memory chip of claim 1 , further comprising:

a third memory cell comprising:

a third pull-up transistor including a fifth gate stack having a fifth gate dielectric layer wrapping around each of a fifth plurality of nanostructures,

a third pull-down transistor including a sixth gate stack having a sixth gate dielectric layer wrapping around each of a sixth plurality of nanostructures,

wherein the fifth gate dielectric layer is free of lanthanum and the sixth gate dielectric layer is doped with lanthanum such that the third memory cell operates at a third threshold voltage, and the second threshold voltage is greater than the third threshold voltage.

7. The semiconductor memory chip of claim 6 ,

wherein the first memory cell and the second memory cell have a first cell size, and the third memory cell has a second cell size,

wherein the second cell size is greater than the first cell size.

8. The semiconductor memory chip of claim 6 ,

wherein each of the sixth plurality of nanostructures in the third memory cell has a greater width along a first direction than each of the second plurality of nanostructures in the first memory cell along the first direction.

9. The semiconductor memory chip of claim 1 ,

wherein a threshold voltage of the first pull-down transistor is lower than a threshold voltage of the second pull-down transistor by at least 30 mV,

wherein a threshold voltage of the first pull-up transistor is lower than a threshold voltage of the second pull-up transistor by at least 30 mV.

10. The semiconductor memory chip of claim 1 ,

wherein the first, the second, the third, and the fourth gate stacks each includes a work function metal layer,

wherein the work function metal layer in the first gate stack is thicker than the work function metal layer in the second gate stack,

wherein the work function metal layer in the third gate stack is thinner than the work function metal layer in the fourth gate stack.

11. A semiconductor memory chip, comprising:

a first memory cell comprising:

a first n-type transistor including a first gate stack having a first gate dielectric layer wrapping around each of a first plurality of nanostructures; and

a second memory cell comprising:

a second n-type transistor including a second gate stack having a second gate dielectric layer wrapping around each of a second plurality of nanostructures,

wherein the first memory cell and the second memory cell have a same first cell length along a first direction and a same first cell width along a second direction perpendicular to the first direction,

wherein the first gate dielectric layer includes more lanthanum dopants than the second gate dielectric layer such that the first n-type transistor has a lower threshold voltage than the second n-type transistor.

12. The semiconductor memory chip of claim 11 ,

wherein the first and the second gate stacks each includes a work function metal layer,

wherein the work function metal layer in the first gate stack is thinner than the work function metal layer in the second gate stack.

13. The semiconductor memory chip of claim 11 ,

wherein a difference between a threshold voltage of the first n-type transistor and a threshold voltage of the second n-type transistor is between about 30 mV and about 120 mV.

14. The semiconductor memory chip of claim 11 , further comprising:

a third memory cell comprising:

a third n-type transistor including a third gate stack having a third gate dielectric layer wrapping around each of a third plurality of nanostructures,

wherein the third gate dielectric layer includes more lanthanum dopants than the second gate dielectric layer such that the third n-type transistor has a lower threshold voltage than the second n-type transistor.

15. The semiconductor memory chip of claim 14 ,

wherein the third memory cell has a third cell length along the first direction and a third cell width along the second direction,

wherein the third cell length is greater than the same first cell length,

wherein the third cell width is about the same as the same first cell width.

16. The semiconductor memory chip of claim 14 , wherein a difference between a threshold voltage of the first n-type transistor and a threshold voltage of the second n-type transistor is between about 30 mV and about 120 mV.

17. A semiconductor memory chip, comprising:

a first memory cell comprising:

a first p-type transistor including a first gate stack having a first gate dielectric layer wrapping around each of a first plurality of nanostructures; and

a second memory cell comprising:

a second p-type transistor including a second gate stack having a second gate dielectric layer wrapping around each of a second plurality of nanostructures,

wherein the first memory cell and the second memory cell have a same first cell length along a first direction and a same first cell width along a second direction perpendicular to the first direction,

wherein the first gate dielectric layer includes less lanthanum dopants than the second gate dielectric layer such that the first p-type transistor has a lower threshold voltage than the second p-type transistor.

18. The semiconductor memory chip of claim 17 ,

wherein the first and the second gate stacks each includes a work function metal layer,

wherein the work function metal layer in the first gate stack is thicker than the work function metal layer in the second gate stack.

19. The semiconductor memory chip of claim 17 ,

wherein a difference between a threshold voltage of the first p-type transistor and a threshold voltage of the second p-type transistor is between about 30 mV and about 120 mV.

20. The semiconductor memory chip of claim 17 ,

wherein the first memory cell further comprises a first n-type transistor including a third gate stack having a third gate dielectric layer wrapping around each of a third plurality of nano structures,

wherein the second memory cell further comprises a second n-type transistor including a fourth gate stack having a fourth gate dielectric layer wrapping around each of a fourth plurality of nanostructures,

wherein the third gate dielectric layer includes more lanthanum dopants than the fourth gate dielectric layer such that the first n-type transistor has a lower threshold voltage than the second n-type transistor.