High electron mobility transistor structure and method of fabricating the same
A high electron mobility transistor includes a substrate. A first III-V compound layer is disposed on the substrate. A second III-V compound layer is embedded within the first III-V compound layer. A P-type gallium nitride gate is embedded within the second III-V compound layer. A gate electrode is disposed on the second III-V compound layer and contacts the P-type gallium nitride gate. A source electrode is disposed at one side of the gate electrode. A drain electrode is disposed at another side of the gate electrode.
1. A high electron mobility transistor structure, comprising
a substrate;
a first III-V compound layer disposed on the substrate;
a second III-V compound layer embedded within the first III-V compound layer, wherein a composition of the first III-V compound layer is different from a composition of the second III-V compound layer;
a P-type gallium nitride gate embedded within the second III-V compound layer, wherein when seeing from a top view, the P-type gallium nitride gate is deviated from a center of the second III-V compound layer;
a gate electrode disposed on the second III-V compound layer and contacting the P-type gallium nitride gate;
a source electrode disposed at one side of the gate electrode, on the second III-V compound layer, and contacting the second III-V compound layer and the first III-V compound layer; and
a drain electrode disposed at another side of the gate electrode, on the second III-V compound layer, and contacting the second III-V compound layer and the first III-V compound layer.
2. The high electron mobility transistor structure of claim 1 , wherein a sectional view of the second III-V compound layer comprises a trapezoid, the trapezoid comprises a upper base, a lower base, and two legs, wherein the upper base is aligned with a top surface of the first III-V compound layer, and the upper base is longer than the lower base.
3. The high electron mobility transistor structure of claim 2 , wherein an obtuse angle is defined between one of the legs and the lower base.
4. The high electron mobility transistor structure of claim 2 , wherein the obtuse angle is between 120 and 150 degrees.
5. The high electron mobility transistor structure of claim 1 , wherein the first III-V compound layer surrounds the second III-V compound layer, and the second III-V compound layer surrounds the P-type gallium nitride gate.
6. The high electron mobility transistor structure of claim 1 , wherein the P-type gallium nitride gate does not contact the first III-V compound layer.
7. The high electron mobility transistor structure of claim 1 , wherein a distance is between a bottom of the P-type gallium nitride gate and the first III-V compound layer, the distance is perpendicular to a top surface of the substrate, and the distance is between 10 and 20 nanometers.
8. The high electron mobility transistor structure of claim 1 , wherein a top surface of the second III-V compound layer, a top surface of the first III-V compound layer and a top surface of the P-type gallium nitride gate are aligned.
9. The high electron mobility transistor structure of claim 1 , wherein a thickness of the second III-V compound layer is between 50 and 100 nanometers.
10. The high electron mobility transistor structure of claim 1 , wherein a distance from a bottom of the second III-V compound layer to a top surface of the substrate is between 2 and 6 micrometers.
11. The high electron mobility transistor structure of claim 1 , wherein two dimensional electron gas generates between the first III-V compound layer and the second III-V compound layer, and the two dimensional electron gas has a trench profile.
12. The high electron mobility transistor structure of claim 1 , wherein the first III-V compound layer is gallium nitride, the second III-V compound layer comprises aluminum gallium nitride, aluminum indium nitride, aluminum indium gallium nitride or aluminum nitride.
13. The high electron mobility transistor structure of claim 1 , further comprising an aluminum nitride layer disposed between the first III-V compound layer and the second III-V compound layer.