Dual-mode high-side power field-effect transistor driver for power regulators
Apparatuses and methods for operating a power converter are described. An integrated circuit can be integrated in a high-side driver of a high-side fiend-effect transistor (FET) of the power converter. The integrated circuit can detect a phase node voltage of a power integrated circuit. The integrated circuit can, in response to the phase node voltage being less than a threshold voltage, operate a high-side FET of the power integrated circuit in a constant-current mode. The integrated circuit can, in response to the phase node voltage being greater than the threshold voltage, operate the high-side FET of the power integrated circuit in a constant-voltage mode.
1. An apparatus comprising:
an integrated circuit configured to:
detect a phase node voltage of a power integrated circuit;
in response to the phase node voltage being less than a threshold voltage before a lapse of a delay, allow the delay to lapse and operate a high-side field-effect transistor (FET) of the power integrated circuit in a constant-current mode, wherein the delay is predefined to limit a dead time of the power integrated circuit; and
in response to the phase node voltage being greater than the threshold voltage before the lapse of the delay, force the delay to lapse and operate the high-side FET of the power integrated circuit in a constant-voltage mode.
2. The apparatus of claim 1 , wherein the integrated circuit comprises:
a first driver circuit configured to operate the high-side FET of the power integrated circuit in the constant-current mode; and
a second driver circuit configured to operate the high-side FET of the power integrated circuit in the constant-voltage mode.
3. The apparatus of claim 2 , wherein the integrated circuit is configured to:
in response to the phase node voltage being less than the threshold voltage, activate the first driver circuit to operate the high-side FET in the constant-current mode; and
deactivate the second driver circuit.
4. The apparatus of claim 3 , wherein the integrated circuit comprises a timer circuit configured to delay an input of a drive signal to the second driver circuit to deactivate the second driver circuit.
5. The apparatus of claim 2 , wherein the integrated circuit is configured to:
in response to the phase node voltage being greater than the threshold voltage, activate the second driver circuit to operate the high-side FET in the constant-voltage mode.
6. The apparatus of claim 5 , wherein the first driver circuit remains activated in response to activation of the second driver circuit.
7. The apparatus of claim 2 , wherein the integrated circuit is configured to, in response to receiving a drive signal for switching off the high-side FET, deactivate the first driver circuit and the second driver circuit.
8. The apparatus of claim 1 , wherein the integrated circuit comprises a phase node detector configured to:
detect the phase node voltage of the power integrated circuit; and
compare the phase node voltage with the threshold voltage.
9. An apparatus comprising:
a power integrated circuit comprising a high-side field-effect transistor (FET) and a low-side FET;
a driver module comprising a high-side driver circuit configured to operate the high-side FET and a low-side driver configured to operate the low-side FET; and
a controller configured to be in communication with the power integrated circuit and the driver module, the controller being configured to:
generate a drive signal for operating the high-side FET; and
send the drive signal to the high-side driver circuit to operate the high-side driver circuit;
wherein the high-side driver circuit being configured to:
detect a phase node voltage of the power integrated circuit;
in response to the phase node voltage being less than a threshold voltage before a lapse of a delay, allow the delay to lapse and operate the high-side FET in a constant-current mode, wherein the delay is predefined to limit a dead time of the power integrated circuit; and
in response to the phase node voltage being greater than the threshold voltage before the lapse of the delay, force the delay to lapse and operate the high-side FET in a constant-voltage mode.
10. The apparatus of claim 9 , wherein the high-side driver circuit comprises:
a first driver circuit configured to operate the high-side FET of the power converter in the constant-current mode; and
a second driver circuit configured to operate the high-side FET of the power converter in the constant-voltage mode.
11. The apparatus of claim 10 , wherein the high-side driver circuit is configured to:
in response to the phase node voltage being less than the threshold voltage, activate the first driver circuit to operate the high-side FET in the constant-current mode; and
deactivate the second driver circuit.
12. The apparatus of claim 11 , wherein the controller is configured to:
generate a drive signal for driving the high-side FET;
send the drive signal to the high-side driver circuit; and
the high-side driver circuit comprises a timer circuit configured to delay an input of the drive signal to the second driver circuit to deactivate the second driver circuit.
13. The apparatus of claim 10 , wherein the high-side driver circuit is configured to:
in response to the phase node voltage being greater than the threshold voltage, activate the second driver circuit to operate the high-side FET in the constant-voltage mode.
14. The apparatus of claim 13 , wherein the first driver circuit is configured to remain activated in response to activation of the second driver circuit.
15. The apparatus of claim 10 , wherein the high-side driver circuit is configured to, in response to the drive signal indicating a switch off of the high-side FET, deactivate the first driver circuit and the second driver circuit.
16. The apparatus of claim 10 , wherein the high-side driver circuit comprises a phase node detector configured to:
detect the phase node voltage of the power integrated circuit; and
compare the phase node voltage with the threshold voltage.
17. A method for operating a power converter, the method comprising:
receiving a drive signal to switch on a high-side field-effect transistor (FET) of a power integrated circuit;
detecting a phase node voltage of a power integrated circuit;
in response to the phase node voltage being less than a threshold voltage before a lapse of a delay, allow the delay to lapse and operating a high-side FET in a constant-current mode, wherein the delay is predefined to limit a dead time of the power integrated circuit; and
in response to the phase node voltage being greater than the threshold voltage before the lapse of the delay, forcing the delay to lapse and operating the high-side FET in a constant-voltage mode.
18. The method of claim 17 , wherein operating the high-side FET in the constant-current mode comprises:
activating a first driver circuit to operate the high-side FET in the constant-current mode; and
deactivate a second driver circuit configured to operate the high-side FET in the constant-voltage mode.
19. The method of claim 18 , wherein deactivating the second driver circuit comprises delaying an input of the drive signal to the second driver circuit.
20. The method of claim 17 , wherein in response to the phase node voltage being greater than the threshold voltage, a first driver circuit configured to operate the high-side FET in the constant-current mode remains activated, and operating the high-side FET in the constant-voltage mode comprises activating a second driver circuit to operate the high-side FET in constant-voltage mode.