Low-jitter digital isolator circuit and digital isolator including the same
View Patent ↗Provided are a low-jitter digital isolator circuit and a digital isolator including the same. The digital isolator circuit includes a signal transmitting module, a signal receiving module, and an isolation channel connected between the signal transmitting module and the signal receiving module. The signal transmitting module is provided with a signal input terminal, and the signal receiving module is provided with a signal output terminal. The signal transmitting module includes a reset circuit, an oscillator and a transmitting circuit which are sequentially connected. The reset circuit is connected to the signal input terminal. The transmitting circuit is connected to the isolation channel. The signal receiving module includes a receiving circuit connected to the isolation channel. In the present invention, signal jitter is reduced, more stable signal transmission and a better isolation effect are achieved, and the area and cost of the digital isolator circuit are reduced.
1. A low-jitter digital isolator circuit, comprising a signal transmitting module, a signal receiving module, and an isolation channel connected between the signal transmitting module and the signal receiving module, wherein the signal transmitting module is provided with a signal input terminal, and the signal receiving module is provided with a signal output terminal;
the signal transmitting module comprises a reset circuit, an oscillator and a transmitting circuit which are sequentially connected, wherein the reset circuit is connected to the signal input terminal and the transmitting circuit is connected to the isolation channel; and the signal receiving module comprises a receiving circuit connected to the isolation channel;
wherein one isolation channel is disposed and the isolation channel comprises a first path and a second path, wherein a first capacitor and a second capacitor are disposed in the first path and a third capacitor and a fourth capacitor are disposed in the second path.
2. The digital isolator circuit according to claim 1 , wherein the reset circuit comprises a first NOT gate, a second NOT gate, an AND gate and an OR gate, wherein:
an input terminal of the first NOT gate is communicated with the signal input terminal and an output terminal of the first NOT gate is communicated with a first input terminal of the OR gate;
an input terminal of the second NOT gate is communicated with the signal input terminal and an output terminal of the second NOT gate is connected to a second input terminal of the AND gate, and a first input terminal of the AND gate is connected to the signal input terminal; and
an output terminal of the AND gate is connected to a second input terminal of the OR gate, and an output terminal of the OR gate is connected to the oscillator.
3. The digital isolator circuit according to claim 2 , wherein the reset circuit comprises a first delayer and a second delayer, wherein the first delayer is connected between the input terminal of the first NOT gate and the signal input terminal, and the second delayer is connected between the first input terminal of the AND gate and the signal input terminal.
4. The digital isolator circuit according to claim 3 , wherein delay duration of the first delayer is longer than delay duration of the second delayer.
5. The digital isolator circuit according to claim 1 , wherein the signal receiving module further comprises a glitch elimination circuit connected between the receiving circuit and the signal output terminal.
6. The digital isolator circuit according to claim 1 , wherein the oscillator comprises a third NOT gate, a fourth NOT gate, a NAND gate, and a feedback branch, wherein:
an input terminal of the third NOT gate is connected to the reset circuit, and an output terminal of the third NOT gate is connected to a second input terminal of the NAND gate;
the feedback branch is connected between a first input terminal of the NAND gate and an output terminal of the NAND gate; and
the output terminal of the NAND gate is connected to an input terminal of the fourth NOT gate, and an output terminal of the fourth NOT gate is connected to the transmitting circuit.
7. The digital isolator circuit according to claim 6 , wherein the feedback branch further comprises a fifth NOT gate and a sixth NOT gate which are sequentially connected in series, wherein an input terminal of the fifth NOT gate is connected to the output terminal of the NAND gate, and an output terminal of the sixth NOT gate is connected to the first input terminal of the NAND gate.
8. A digital isolator, comprising the digital isolator circuit according to claim 1 .