IP Library › Granted Patent US 12,058,358
Granted Patent B2
US 12,058,358 · App. 17/512,584 · Granted Aug 6, 2024

Video signal processing method and apparatus using adaptive motion vector resolution

Inventors: Geonjung Ko (Seoul, KR); Dongcheol Kim (Suwon-Si, KR); Juhyung Son (Uiwang-Si, KR); Jaehong Jung (Seoul, KR); Jinsam Kwak (Uiwang-si, KR)
Assignee: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.
H04N19/46H04N19/105H04N19/137H04N19/159H04N19/176
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Quick Facts
Patent No.
US 12,058,358
App. No.
17/512,584
Granted
Aug 6, 2024
Kind
B2
Abstract

The present disclosure relates to a method and apparatus for processing a video signal and, more specifically, comprises the steps of: parsing, from a bitstream, an adaptive motion vector resolution (AMVR) enabled flag (sps_amvr_enabled_flag) indicating whether or not adaptive motion vector differential resolution is used; parsing, from the bitstream, an affine enabled flag (sps_affine_enabled_flag) indicating whether or not affine motion compensation is usable; on the basis of the affine enabled flag, determining whether or not the affine motion compensation is usable; when the affine motion compensation is usable, determining, on the basis of the AMVR enabled flag, whether or not the adaptive motion vector differential resolution is used; and, when the adaptive motion vector differential resolution is used, parsing, from the bitstream, an affine AMVR enabled flag (sps_affine_amvr_enabled flag) indicating whether or not the adaptive motion vector differential resolution is usable for the affine motion compensation.

Claims (72)

1. A method for processing a video signal, comprising:

parsing, from a bitstream, a first syntax element indicating whether adaptive motion vector differential resolution is enabled; and

parsing, from the bitstream, a second syntax element indicating whether affine motion compensation is enabled;

when the first syntax element indicates that the adaptive motion vector differential resolution is enabled and the second syntax element indicates that the affine motion compensation is enabled, parsing, from the bitstream, a third syntax element indicating whether the adaptive motion vector differential resolution is enabled for the affine motion compensation.

2. The method of claim 1 ,

wherein at least one of the first syntax element, the second syntax element, and/or the third syntax element is signaled as a sequence unit.

3. The method of claim 1 ,

wherein, when the first syntax element indicates that the adaptive motion vector differential resolution is not enabled and the second syntax element indicates that the affine motion compensation is enabled, a value of the third syntax element is inferred as a value indicating that the adaptive motion vector differential resolution is not enabled for the affine motion compensation.

4. The method of claim 1 ,

wherein, when the second syntax element indicates that the affine motion compensation is not enabled, a value of the third syntax element is inferred as a value indicating that the adaptive motion vector differential resolution is not enabled for the affine motion compensation.

5. The method of claim 1 , the method further comprising:

parsing, from the bitstream, a fourth syntax element indicating whether the affine motion compensation is used for a current block;

when the first syntax element indicates that the adaptive motion vector differential resolution is enabled, the fourth syntax element indicates that the affine motion compensation is not used for the current block and at least one of a plurality of motion vector differences for the current block is non-zero, parsing, from the bitstream, a fifth syntax element indicating a resolution of a motion vector difference; and

modifying the plurality of motion vector differences for the current block on the basis of the fifth syntax element.

6. The method of claim 1 , the method further comprising:

parsing, from the bitstream, a fourth syntax element indicating whether the affine motion compensation is used for a current block;

when the third syntax element indicates that the adaptive motion vector differential resolution is enabled for the affine motion compensation, the fourth syntax element indicates that the affine motion compensation is used for the current block and at least one of a plurality of control point motion vector differences for the current block is non-zero, parsing, from the bitstream, a fifth syntax element indicating a resolution of a motion vector difference; and

modifying the plurality of control point motion vector differences for the current block on the basis of the fifth syntax element.

7. The method of claim 1 , the method further comprising:

parsing, from the bitstream, a sixth syntax element related to a reference picture list for a current block,

when the sixth syntax element indicates that a reference picture list other than a reference picture list 0 is available, parsing, from the bitstream, a seventh syntax element indicating a motion vector predictor index of a reference picture list 1.

8. The method of claim 7 , the method further comprising:

parsing, from the bitstream, an eighth syntax element indicating whether a motion vector difference and a plurality of control point motion vector differences are set to zero for the reference picture list 1,

wherein the seventh syntax element is parsed regardless of the eighth syntax element.

9. A decoding apparatus for processing a video signal, the decoding apparatus comprising:

a processor,

wherein the processor is configured to:

parse, from a bitstream, a first syntax element indicating whether adaptive motion vector differential resolution is enabled,

parse, from the bitstream, a second syntax element indicating whether affine motion compensation is enabled, and

when the first syntax element indicates that the adaptive motion vector differential resolution is enabled and the second syntax element indicates that the affine motion compensation is enabled, parse, from the bitstream, a third syntax element indicating whether the adaptive motion vector differential resolution is enabled for the affine motion compensation.

10. The decoding apparatus of claim 9 ,

wherein at least one of the first syntax element, the second syntax element, and/or the third syntax element is signaled as a sequence unit.

11. The decoding apparatus of claim 9 ,

wherein, when the

first syntax element indicates that the adaptive motion vector differential resolution is not enabled and the second syntax element indicates that the affine motion compensation is enabled, a value of the third syntax element is inferred as a value indicating that the adaptive motion vector differential resolution is not enabled for the affine motion compensation.

12. The decoding apparatus of claim 9 ,

wherein, when the second syntax element indicates that the affine motion compensation is not enabled, a value of the third syntax element is inferred as a value indicating that the adaptive motion vector differential resolution is not enabled for the affine motion compensation.

13. The decoding apparatus of claim 9 ,

wherein the processor is configured to:

parse, from the bitstream, a fourth syntax element indicating whether the affine motion compensation is used for a current block,

when the first syntax element indicates that the adaptive motion vector differential resolution is enabled, the fourth syntax element indicates that the affine motion compensation is not used for the current block and at least one of a plurality of motion vector differences for the current block is non-zero, parse, from the bitstream, a fifth syntax element indicating a resolution of a motion vector difference, and

modify the plurality of motion vector differences for the current block on the basis of the fifth syntax element.

14. The decoding apparatus of claim 9 ,

wherein the processor is configured to:

parse, from the bitstream, a fourth syntax element indicating whether the affine motion compensation is used for a current block,

when the third syntax element indicates that the adaptive motion vector differential resolution is enabled for the affine motion compensation, the fourth syntax element indicates that the affine motion compensation is used for the current block and at least one of a plurality of control point motion vector differences for the current block is non-zero, parse, from the bitstream, a fifth syntax element indicating a resolution of a motion vector difference, and

modify the plurality of control point motion vector differences for the current block on the basis of the fifth syntax element.

15. The decoding apparatus of claim 9 ,

wherein the processor is configured to:

parse, from the bitstream, a sixth syntax element related to a reference picture list for a current block,

when the sixth syntax element indicates that a reference picture list other than a reference picture list 0 is available, parse, from the bitstream, a seventh syntax element indicating a motion vector predictor index of a reference picture list 1.

16. The decoding apparatus of claim 15 ,

wherein the processor is configured to:

parse, from the bitstream, an eighth syntax element indicating whether a motion vector difference and a plurality of control point motion vector differences are set to zero for the reference picture list 1,

wherein the seventh syntax element is parsed regardless of the eighth syntax element.

17. An encoding apparatus for processing a video signal, the encoding apparatus comprising:

a processor,

wherein the processor is configured to

obtain a bitstream to be decoded by a decoder using a decoding method,

wherein the decoding method comprising:

parsing, from the bitstream, a first syntax element indicating whether adaptive motion vector differential resolution is enabled;

parsing, from the bitstream, a second syntax element indicating whether affine motion compensation is enabled; and

when the first syntax element indicates that the adaptive motion vector differential resolution is enabled and the second syntax element indicates that the affine motion compensation is enabled, parsing, from the bitstream, a third syntax element indicating whether the adaptive motion vector differential resolution is enabled for the affine motion compensation.

18. The encoding apparatus of claim 17 ,

wherein at least one of the first syntax element, the second syntax element, and/or the third syntax element is signaled as a sequence unit.

19. The encoding apparatus of claim 17 ,

wherein when the first syntax element indicates that the adaptive motion vector differential resolution is not enabled and the second syntax element indicates that the affine motion compensation is enabled, a value of the third syntax element is inferred as a value indicating that the adaptive motion vector differential resolution is not enabled for the affine motion compensation.

20. A method for generating bitstream, comprising:

generating a first syntax element indicating whether adaptive motion vector differential resolution is enabled;

generating a second syntax element indicating whether affine motion compensation is enabled;

when the first syntax element indicates that the adaptive motion vector differential resolution is enabled and the second syntax element indicates that the affine motion compensation is enabled, generating a third syntax element indicating whether the adaptive motion vector differential resolution is enabled for the affine motion compensation; and

generating a bitstream including at least one of the first syntax element, the second syntax element, and/or the third syntax element.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2022
From: HUMAX CO., LTD.
To: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.
Reel/Frame 060456/0571 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2021
From: KO, GEONJUNG; KIM, DONGCHEOL; SON, JUHYUNG; JUNG, JAEHONG; KWAK, JINSAM
To: WILUS INSTITUTE OF STANDARDS AND TECHNOLOGY INC.; HUMAX CO., LTD.
Reel/Frame 057939/0129 →
Priority Claims (3)
KR 10-2019-0050960 · Apr 30, 2019 · national
KR 10-2019-0057185 · May 15, 2019 · national
KR 10-2019-0057650 · May 17, 2019 · national
Continuity (2)
Continuation PCTKR2020005830 · May 4, 2020
Related Publication 20220053206A1 · Feb 17, 2022