Three-dimensional memory devices and fabricating methods thereof
A method for forming a 3D memory device is disclosed. The method includes forming an alternating dielectric stack on a substrate. Then a plurality of channel structures and dummy channel structures vertically penetrating the alternating dielectric stack are formed, The channel structures are located in a core region, and the dummy channel structures are located in a staircase region. A gate line silt structure is formed vertically penetrating the alternating dielectric stack and laterally extending in a first direction. The gate line silt structure includes a narrow portion that has a reduced width along a second direction different from the first direction.
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming an alternating dielectric stack on a substrate;
forming a plurality of channel structures and dummy channel structures vertically penetrating the alternating dielectric stack, wherein the channel structures are located in a core region, and the dummy channel structures are located in a staircase region; and
forming a gate line slit structure vertically penetrating the alternating dielectric stack, laterally extending in a first direction, and, at least in the core region, having a first width defined along a second direction different from the first direction;
wherein the gate line slit structure includes a narrow portion that has a reduced width less than the first width, and wherein the narrow portion is disposed adjacent to a boundary of the core region and the staircase region.
2. The method of claim 1 , wherein forming the gate line slit structure comprises:
patterning a mask layer to form an opening extending in the first direction on the alternating dielectric stack, wherein the opening includes a narrow portion having a reduced width along the second direction;
using the patterned mask layer to form a gate line slit vertically penetrating the alternating dielectric stack; and
forming the gate line slit structure in the gate line slit.
3. The method of claim 2 , wherein forming the gate line slit comprises:
etching the alternating dielectric stack based on the patterned mask layer to form the gate line slit, such that a narrow portion of the formed gate line slit is close to a transition area of the core region and the staircase region.
4. The method of claim 2 , wherein forming the gate line slit structure comprises:
forming a doped region in the substrate at a bottom of the gate line slit;
forming two spacer layers on both sidewalls of the gate line slit; and
forming a conductive wall between the two spacer layers, wherein the conductive wall is electrically in contact with the doped region.
5. The method of claim 2 , wherein forming the gate line slit structure comprises:
forming the gate line slit structure in the gate line slit, such that a distance between the gate line slit structure and at least two channel structures that are adjacent to the gate line slit structure and close to a transition area of the core region and the staircase region is not less than about 120 nm.
6. The method of claim 1 , wherein forming the alternating dielectric stack comprises:
forming at least 64 dielectric layer pairs stacked in a vertical direction, wherein each dielectric layer pair includes a first dielectric layer and a second dielectric layer that is different from the first dielectric layer.
7. The method of claim 1 , wherein forming the plurality of channel structures and dummy channel structures comprises:
simultaneously forming a plurality of channel holes vertically penetrating the alternating dielectric stack, wherein a first subset of channel holes in the core region are arranged in a staggered array form, and a second subset of channel holes in the staircase region are arranged in an array form; and
simultaneously forming the channel structures in the first subset of channel holes and the dummy channel structures in the second subset of channel holes.
8. The method of claim 7 , wherein simultaneously forming the plurality of channel structures and dummy channel structures comprises:
forming an epitaxial layer on a surface of the substrate that is exposed by each channel hole;
forming a functional layer on sidewalls of each channel hole, followed by;
forming a channel layer covering the functional layer and in contact with the epitaxial layer in each channel hole, followed by;
forming a dielectric filling structure filling each channel hole, followed by; and
forming a channel plug on a top portion of each channel hole and on the dielectric filling structure.
9. The method of claim 6 , before forming the gate line slit structure in the gate line slit, further comprising:
replacing the second dielectric layers in the alternating dielectric stack with conductive layers through the gate line slit.
10. The method of claim 9 , wherein replacing the second dielectric layers in the alternating dielectric with conductive layers comprises:
removing the second dielectric layers in the alternating dielectric stack through the gate line slit to form a plurality of horizontal trenches; and
forming the conductive layers in the plurality of horizontal trenches.
11. A three-dimensional (3D) memory device, comprising:
an alternating conductive/dielectric stack on a substrate;
a plurality of channel structures and dummy channel structures vertically penetrating the alternating conductive/dielectric stack, wherein the channel structures are located in a core region, and the dummy channel structures are located in a staircase region; and
a gate line slit structure vertically penetrating the alternating conductive/dielectric stack, laterally extending in a first direction in the core region and the staircase region, and having a first width defined along a second direction different from the first direction;
wherein the gate line slit structure includes a narrow portion that has a reduced width less than the first width, and wherein the narrow portion is disposed adjacent to a boundary of the core region and the staircase region and is between portions of the gate line slit structure having the first width.
12. The device of claim 11 , wherein the first direction is a word line direction, and the second direction is a bit line direction.
13. The device of claim 11 , wherein the reduced width of the narrow portion of the gate line slit structure is at least 40 nm less than a normal width of a normal portion of the gate line slit structure.
14. The device of claim 11 , wherein the reduced width of the narrow portion of the gate line slit structure is at least 70 nm.
15. The device of claim 11 , wherein a length of the narrow portion of the gate line slit structure along the first direction is not less than two times a diameter of the channel structures plus a distance between two adjacent channel structures.
16. The device of claim 11 , wherein a length of the narrow portion of the gate line slit structure along the first direction is not less than a range between 300 nm to 500 nm.
17. The device of claim 11 , wherein the gate line slit structure comprises a conductive wall between two spacer layers and is electrically in contact with a doped region of the substrate.
18. The device of claim 11 , wherein a distance between the gate line slit structure and at least two channel structures that are adjacent to the gate line slit structure and close to a transition area of the core region and the staircase region is not less than about 120 nm.
19. The device of claim 11 , wherein the alternating dielectric stack comprises at least 64 conductive/dielectric layer pairs stacked in a vertical direction.
20. The device of claim 11 , wherein each channel structure comprises:
an epitaxial layer on a bottom portion of a channel hole;
a functional layer on a sidewall of the channel hole;
a channel layer covering the functional layer and in contact with the epitaxial layer;
a dielectric filling structure filling the channel hole; and
a channel plug on a top portion of the channel hole and on the dielectric filling structure.