Three-dimensional memory devices with support structures and methods for forming the same

1. A three-dimensional (3D) memory device, comprising:

a memory stack comprising a plurality of conductor/dielectric layer pairs, on a substrate, comprising a core region and a non-core region neighboring the core region; and

a support structure extending through the memory stack in the non-core region and into the substrate, wherein

the support structure comprises a first support portion and a second support portion over the first support portion, the first support portion having a stiffness higher than the second support portion, the first support portion penetrating a low subset of the conductor/dielectric layer pairs and being in contact with the substrate, and the second support portion penetrating an upper subset of the conductor/dielectric layer pairs and being in contact with a top surface of the first support portion;

the first support portion is located at a lower portion of the support structure, and the second support portion is located at an upper portion and the lower portion of the support structure; and

the second support portion of the support structure is on and laterally surrounds the first support portion of the support structure.

2. The memory device of claim 1 , wherein the first support portion comprises polysilicon and the second support portion comprises silicon oxide.

3. The memory device of claim 1 , wherein the non-core region comprises a staircase region neighboring the core region and a transitional region between the core region and the staircase region.

4. The memory device of claim 3 , wherein the support structure is located in the transitional region.

5. The memory device of claim 4 , further comprising, in the staircase region, a second support structure extending in a staircase structure and an insulating structure over the staircase structure, wherein:

the second support structure comprises a first support portion of the second support structure and a second support portion of the second support structure over the first support portion of the second support structure, the first support portion of the second support structure having a stiffness higher than the second support portion of the second support structure.

6. The memory device of claim 5 , wherein the first support portion of the second support structure comprises polysilicon, and the second support portion of the second support structure comprises silicon oxide.

7. The memory device of claim 5 , wherein

the first support portion of the second support structure is located at a lower portion of the second support structure, and the second support portion of the second support structure is located at an upper portion of the second support structure; and

the second support portion of the second support structure is on the first support portion of the second support structure.

8. The memory device of claim 5 , wherein

the first support portion of the second support structure is located at a lower portion of the second support structure, and the second support portion of the second support structure is located at an upper portion and the lower portion of the second support structure; and

the second support portion of the second support structure is on and laterally surrounds the first support portion of the second support structure.

9. The memory device of claim 3 , wherein the support structure is located in a staircase structure in the staircase region and an insulating structure over the staircase structure.

10. The memory device of claim 9 , further comprising a second support structure extending in the transitional region, wherein:

the second support structure comprises a first support portion of the second support structure and a second support portion of the second support structure over the first support portion of the second support structure, the first support portion of the second support structure having a stiffness higher than the second support portion of the second support structure; and

the first support portion of the second support structure comprises polysilicon, and the second support portion of the second support structure comprises silicon oxide.

11. A memory device, comprising:

a memory stack comprising a plurality of conductor/dielectric layer pairs, on a substrate; and

at least one support structure each comprising:

a first support portion penetrating a low subset of the conductor/dielectric layer pairs, being in contact with the substrate, and having a first material, and

a second support portion penetrating an upper subset of the conductor/dielectric layer pairs, being in contact with a top surface of the first support portion, and having a second material,

wherein a first stiffness of the first material is higher than a second stiffness of the second material, and the second support portion is in contact with a sidewall of the first support portion.

12. The memory device of claim 11 , wherein:

the first support portion extends into the substrate.

13. The memory device of claim 11 , wherein:

the second support portion extends into the substrate.

14. The memory device of claim 11 , wherein:

a lower portion of the second support portion laterally surrounds an upper portion of the first support portion.

15. The memory device of claim 11 , further comprising:

a channel structure in a core region;

wherein the at least one support structure is located in a non-core region.

16. The memory device of claim 15 , wherein the at least one support structure comprises:

a first support structure located in a transitional region between the core region and a staircase region; and

a second support structure located in the staircase region.

17. The memory device of claim 16 , further comprising:

a third support structure located in the staircase region, wherein the third support structure includes the second material without the first material.