Semiconductor memory devices with arrays of vias and methods of manufacturing thereof

1. A semiconductor die, comprising:

a device portion comprising an array of semiconductor devices extending in a first direction; and

at least one interface portion located adjacent to an axial end of the device portion in the first direction, the interface portion having a staircase profile in a vertical direction, the interface portion comprising:

a stack comprising a plurality of gate layers and a plurality of insulating layers alternatively stacked on top of one another,

a memory layer interposed between each of the plurality of gate layers and the plurality of insulating layers,

an array of gate vias, each of the array of gate vias coupled to a corresponding gate layer of the plurality of gate layers through the memory layer, and

an array of interface vias disposed adjacent to the array of gates gate vias in a second direction perpendicular to the first direction.

2. The semiconductor die of claim 1 , wherein the memory layer is disposed on at least a top surface and a bottom surface of each of the plurality of gate layers.

3. The semiconductor die of claim 1 , wherein:

the interface portion further comprises an interlayer dielectric disposed on the stack, and

the array of gate vias are defined through the interlayer dielectric.

4. The semiconductor die of claim 1 , wherein each interface via of the array of interface vias is electrically coupled to a corresponding gate via of the array of gate vias.

5. The semiconductor die of claim 4 , wherein:

the at least one interface portion comprises a plurality of stacks disposed parallel to each other in the second direction, each stack of the plurality of stacks corresponding to a set of semiconductor devices included in the array of semiconductor devices, and

the semiconductor die further comprises an insulation structure interposed between adjacent stacks of the plurality of stacks in the second direction.

6. The semiconductor die of claim 5 , wherein the interface vias are defined through the insulator structure.

7. The semiconductor die of claim 4 , wherein each of the array of gate vias and each of the array of interface vias have a polygonal cross-sectional shape.

8. The semiconductor die of claim 4 , wherein each of the array of gate vias has a polygonal cross-sectional shape, and each of the array of interface vias has a closed non-polygonal two-dimensional cross-sectional shape.

9. The semiconductor die of claim 4 , wherein each of the array of interface vias has a polygonal cross-sectional shape, and each of the array of gate vias has a closed non-polygonal two-dimensional cross-sectional shape.

10. The semiconductor die of claim 4 , wherein each interface via of the array of interface vias is axially offset from an adjacent gate via of the array of gate vias in the first direction.

11. A semiconductor die, comprising:

a device portion comprising an array of semiconductor devices extending in a first direction; and

at least one interface portion located adjacent to an axial end of the device portion in the first direction, the interface portion having a staircase profile in a vertical direction, the interface portion comprising:

a stack comprising a plurality of gate layers and a plurality of insulating layers alternatively stacked on top of one another,

a memory layer interposed surrounding each of the plurality of gate layers,

an array of gate vias, each of the array of gate vias coupled to a corresponding gate layer of the plurality of gate layers through the memory layer, and

an array of interface vias disposed adjacent to the array of gates gate vias in a second direction perpendicular to the first direction.

12. The semiconductor die of claim 11 , wherein the memory layer includes a ferroelectric material.

13. The semiconductor die of claim 11 , wherein:

the interface portion further comprises an interlayer dielectric disposed on the stack, and

the array of gate vias are defined through the interlayer dielectric.

14. The semiconductor die of claim 11 , wherein each interface via of the array of interface vias is electrically coupled to a corresponding gate via of the array of gate vias.

15. The semiconductor die of claim 14 , further comprising:

a plurality of through via caps electrically couple each of the interface vias to a corresponding one of the gate vias, wherein each of the through via caps extends in the second direction.

16. The semiconductor die of claim 15 , wherein the plurality of through via caps are disposed above the array of gate vias and the array of interface vias.

17. The semiconductor die of claim 11 , wherein each of the array of gate vias and each of the array of interface vias have a polygonal cross-sectional shape.

18. The semiconductor die of claim 11 , wherein each of the array of gate vias has a polygonal cross-sectional shape, and each of the array of interface vias has a closed non-polygonal two-dimensional cross-sectional shape.

19. A semiconductor die, comprising:

a device portion comprising an array of semiconductor devices extending in a first direction; and

at least one interface portion located adjacent to an axial end of the device portion in the first direction, the interface portion having a staircase profile in a vertical direction, the interface portion comprising:

a stack comprising a plurality of gate layers and a plurality of insulating layers alternatively stacked on top of one another,

a memory layer interposed surrounding each of the plurality of gate layers and including a ferroelectric material,

an array of gate vias, each of the array of gate vias coupled to a corresponding gate layer of the plurality of gate layers through the memory layer, and

an array of interface vias disposed adjacent to the array of gates gate vias in a second direction perpendicular to the first direction.

20. The semiconductor die of claim 19 , wherein each interface via of the array of interface vias is electrically coupled to a corresponding gate via of the array of gate vias.