Power control circuit and control method

1. A power control circuit, comprising:

a control module circuit configured to control, according to an activation command, a memory bank of a plurality of memory banks to perform an operation;

a plurality of power management module circuits configured to wake up a local power supply for the memory bank according to a clock enable signal;

a power control module circuit communicatively coupled with the plurality of power management module circuits and configured to:

send the clock enable signal to a power management module circuit of the plurality of power management circuits corresponding to the memory bank corresponding to the activation command in a power-saving mode, and

send the clock enable signal to the plurality of power management module circuits corresponding to the plurality of memory banks in a non-power-saving mode, wherein the power-saving mode indicates that a system clock is in a low-frequency state, wherein in the low-frequency state, a clock cycle of the system clock is not shorter than a duration of a normalized signal indicating a time length required for waking up the memory bank corresponding to the activation command; and

a state determining module circuit communicatively coupled with the power control module circuit and configured to control the power control module circuit to switch to the power-saving mode or the non-power-saving mode based on the system clock and the normalized signal by:

sending a first signal to the power control module circuit to instruct the power control module circuit to switch to the power-saving mode; and

sending a second signal to the power control module circuit to instruct the power control module circuit to switch to the non-power-saving mode,

wherein the state determining module circuit comprises a signal generation unit circuit, a comparison unit circuit, and an output unit circuit, the signal generation unit circuit is configured to generate the normalized signal based on the system clock; the comparison unit circuit is communicatively coupled with the signal generation unit circuit and is configured to compare the clock cycle of the system clock with the duration of the normalized signal; and the output unit circuit is communicatively coupled with the comparison unit circuit and the power control module circuit and is configured to output the first signal or the second signal based on an output result of the comparison unit circuit.

2. The power control circuit of claim 1 , wherein:

the signal generation unit circuit comprises a sampling circuit and a delay circuit;

the sampling circuit is configured to generate a pulse signal based on a flipping edge of the system clock; and

the delay circuit is communicatively coupled with the sampling circuit and is configured to delay the pulse signal and output the normalized signal.

3. The power control circuit of claim 2 , wherein the delay circuit comprises a plurality of stages of delay circuits, and the stages of delay circuits output a plurality of normalized signals including the normalized signal.

4. The power control circuit of claim 3 , wherein the comparison unit circuit comprises a plurality of comparison subunit circuits, respectively communicatively coupled with the stages of delay circuits and configured to compare the clock cycle of the system clock with the durations of the normalized signals output by the stages of delay circuits; and

the output unit circuit is configured to output the first signal or the second signal based on an output result of the comparison subunit circuits.

5. The power control circuit of claim 4 , wherein:

comparing the clock cycle of the system clock with the durations of the normalized signals comprises comparing a pulse width of the system clock with pulse widths of the normalized signals,

the state determining module circuit is configured to send the first signal to the power control module circuit in response to the pulse widths of the normalized signals being narrower than the pulse width of the system clock, and

the state determining module circuit is configured to send the second signal to the power control module circuit in response to the pulse widths of the normalized signals being wider than the pulse width of the system clock.

6. The power control circuit of claim 1 , wherein the activation command is output to a control module circuit of a memory bank at a corresponding address after the address is decoded by a command decoding control module circuit.

7. The power control circuit of claim 1 , wherein in the power-saving mode, the power control module circuit is configured to send the clock enable signal to the power management module circuit corresponding to the memory bank corresponding to the activation command by controlling a port that outputs the clock enable signal.

8. The power control circuit of claim 1 , further comprising a plurality of controllable switches, each of the plurality of controllable switches being between the power control module circuit and each of the plurality of power management module circuits corresponding to the plurality of memory banks,

wherein in the power-saving mode, the power control module circuit is configured to send the clock enable signal to the power management module circuit corresponding to the memory bank corresponding to the activation command by controlling at least some of the plurality of controllable switches to be on or off.

9. A power control method, applicable to a power control circuit comprising a control module circuit, a plurality of power management module circuits, a power control module circuit, and a state determining module circuit, comprising:

controlling, by the control module circuit according to an activation command, a memory bank of a plurality of memory banks to perform an operation;

waking up, by the plurality of power management module circuits, a local power supply for the memory bank according to a clock enable signal;

sending, by the power control module circuit, the clock enable signal to a power management module circuit of the plurality of power management circuits corresponding to the memory bank corresponding to the activation command in response to a power-saving mode;

sending, by the power control module circuit, the clock enable signal to the plurality of power management module circuits corresponding to the plurality of memory banks in response to a non-power-saving mode, wherein the power-saving mode indicates that a system clock is in a low-frequency state, wherein in the low-frequency state, a clock cycle of the system clock is not shorter than a duration of a normalized signal indicating a time length required for waking up the memory bank corresponding to the activation command; and

controlling, by the state determining module circuit, the power control module circuit to switch to the power-saving mode or the non-power-saving mode based on the system clock and the normalized signal by:

sending, by the state determining module circuit, a first signal to the power control module circuit to instruct the power control module circuit to switch to the power-saving mode; or

sending, by the state determining module circuit, a second signal to the power control module circuit to instruct the power control module circuit to switch to the non-power-saving mode,

wherein the state determining module circuit comprises a signal generation unit circuit, a comparison unit circuit, and an output unit circuit, and the method further comprises:

generating, by the signal generation unit circuit, the normalized signal based on the system clock;

comparing, by the comparison unit circuit, the clock cycle of the system clock with the normalized signal; and

outputting, by the output unit circuit, the first signal or the second signal based on an output result of the comparison unit circuit.

10. The method of claim 9 , wherein:

the signal generation unit circuit comprises a sampling circuit and a delay circuit;

the sampling circuit is configured to generate a pulse signal based on a flipping edge of the system clock; and

the delay circuit is communicatively coupled with the sampling circuit and is configured to delay the pulse signal and output the normalized signal.

11. The method of claim 10 , wherein the delay circuit comprises a plurality of stages of delay circuits configured to output a plurality of normalized signals including the normalized signal, and the comparison unit circuit comprises a plurality of comparison subunit circuits, and the method further comprises:

comparing, by the comparison subunit circuits, the clock cycle of the system clock with the durations of the normalized signals output by the stages of delay circuits; and

outputting, by the output unit circuit, the first signal or the second signal based on an output result of the comparison subunit circuits.

12. The method of claim 11 , wherein comparing the clock cycle of the system clock with the durations of the normalized signals comprises comparing a pulse width of the system clock with pulse widths of the normalized signals, and the method further comprises:

sending, by the state determining module circuit, the first signal to the power control module circuit in response to the pulse widths of the normalized signals being narrower than the pulse width of the system clock; and

sending, by the state determining module circuit, the second signal to the power control module circuit in response to the pulse widths of the normalized signals being wider than the pulse width of the system clock.