Semiconductor device including combination rows and method and system for generating layout diagram of same

1. A method of manufacturing a semiconductor device, for a layout diagram stored on a non-transitory computer-readable medium, the method comprising generating the layout diagram including:

arranging the layout diagram into rows which extend substantially in a first direction, the rows including a first row and a second row, the second row being adjacent to the first row in a second direction substantially perpendicular to the first direction;

configuring one or more of the rows as combination rows, the combination-row-configuring including:

configuring the second row as a combination row;

relative to the second direction, setting a height of each of the one or more combination rows to be substantially equal to a sum of a first height of a first cell and a second height of a second cell, the first cell being different than the second cell, and the first height being different than the second height; and

populating each of the one or more combination rows including:

within the second row and relative to the second direction, stacking a first instance of the first cell on a first instance of the second cell such that the first instance of the first cell is between the first row and the first instance of the second cell; and

within the second row and relative to the second direction, stacking a second instance of the second cell on a second instance of the first cell such that the second instance of the second cell is between the first row and the second instance of the first cell.

2. The method of claim 1 , wherein the generating the layout diagram further includes:

configuring each of the first and second cells including:

generating an active area pattern extending in the first direction; and

generating a gate pattern extending in the second direction and overlapping the active area pattern,

the method further comprising, based on the layout diagram, at least one of:

(A) making one or more photolithographic exposures;

(B) fabricating one or more semiconductor masks; or

(C) fabricating at least one component in a layer of a semiconductor integrated circuit.

3. The method of claim 1 , wherein:

the first cell is a high power (HP) cell and the second cell is a low power (LP) cell; or

the first cell is an LP cell and the second cell is an HP cell.

4. The method of claim 1 , wherein the populating further includes:

within at least one of the one or more combination rows and relative the second direction:

stacking a third instance of the first cell on a third instance of the second cell resulting in a 1st cell/2nd cell stack; and

configuring the 1st cell/2nd cell stack as an integral cell; or

within at least one of the one or more combination rows and relative the second direction:

stacking a fourth instance of the second cell on a fourth instance of the first cell resulting in a 2nd cell/1st cell stack; and

configuring the 2nd cell/1st cell stack as an integral cell.

5. The method of claim 1 , the generating the layout diagram further includes:

configuring one or more rows as first-cell-only rows, the first-cell-only configuring including:

relative to the second direction, setting a height of each of the one or more first-cell-only rows to be substantially equal to the first height of the first cell;

relative to the second direction, interspersing the one or more first-cell-only rows among the one or more combination rows; and

populating each of the one or more first-cell-only rows including:

within each of the one or more first-cell-only rows, inserting another instance of the first cell.

6. The method of claim 5 , the generating the layout diagram further includes:

configuring one or more rows as second-cell-only rows, the second-cell-only configuring including:

relative to the second direction, setting a height of each of the one or more second-cell-only rows to be substantially equal to the second height of the second cell;

interspersing the one or more second-cell-only rows among the one or more combination rows and among the one or more first-cell-only rows; and

populating each of the one or more second-cell-only rows including:

within each of the one or more second-cell-only rows, inserting at least another instance of the second cell.

7. The method of claim 1 , the generating the layout diagram further includes:

configuring one or more rows as second-cell only rows, the second-cell-only configuring including:

relative to the second direction, setting a height of each of the one or more second-cell-only rows to be substantially equal to the second height of the second cell;

interspersing the one or more second-cell-only rows among the one or more combination rows; and

populating each of the one or more second-cell-only rows including:

within each of the one or more second-cell-only rows, inserting at least another instance of the second cell.

8. The method of claim 1 , wherein the generating the layout diagram further includes:

configuring each of the first and second cells including:

generating conductive patterns for a first metallization level (M_1st level) and having corresponding long axes extending substantially in the first direction;

relative to the second direction, setting a first pitch as a sole pitch for the M_1st level, the first pitch being for conductive patterns;

generating conductive patterns for a second metallization level (M_2nd level);

generating conductive patterns for a third metallization level (M_3rd level) including conductive patterns for a power grid (PG patterns) and conductive patterns for control or data signals (logic patterns); and

relative to the second direction, setting multiple pitches for the M_3rd level, the multiple pitches including:

a second pitch for logic patterns; and

a third pitch for PG patterns, the third pitch being greater than the second pitch.

9. A method of manufacturing a semiconductor device, for a layout diagram stored on a non-transitory computer-readable medium, the method comprising generating the layout diagram including:

arranging the layout diagram into rows which extend substantially in a first direction; and

configuring first and second cells for the rows including:

generating conductive patterns for a first metallization level (M_1st level);

relative to a second direction substantially perpendicular to the first direction, setting a first pitch as a sole pitch for the M_1st level, the first pitch being for conductive patterns;

generating conductive patterns for a second metallization level (M_2nd level);

generating conductive patterns for a third metallization level (M_3rd level) including conductive patterns for a power grid (PG patterns) and conductive patterns for control or data signals (logic patterns); and

relative to the second direction, setting multiple pitches for the M_3rd level, the multiple pitches including:

a second pitch for logic patterns, the second pitch being different from the first pitch; and

a third pitch for PG patterns, the third pitch being greater than the second pitch.

10. The method of claim 9 , further comprising:

based on the layout diagram, at least one of:

(A) making one or more photolithographic exposures;

(B) fabricating one or more semiconductor masks; or

(C) fabricating at least one component in a layer of a semiconductor integrated circuit.

11. The method of claim 9 , wherein the rows include a first row and a second row, the second row being adjacent to the first row in the second direction,

the generating the layout diagram further includes:

configuring one or more of the rows as combination rows including:

configuring the second row as a combination row;

relative to the second direction, setting a height of each of the one or more combination rows to be substantially equal to a sum of a first height of a first cell and a second height of a second cell, the first cell being different than the second cell, and the first height being different than the second height; and

populating each of the one or more combination rows including:

within the second row and relative to the second direction, stacking a first instance of the first cell on a first instance of the second cell such that the first instance of the first cell is between the first row and the first instance of the second cell; and

within the second row and relative to the second direction, stacking a second instance of the second cell on a second instance of the first cell such that the second instance of the second cell is between the first row and the second instance of the first cell.

12. The method of claim 11 , wherein:

the first cell is a high power (HP) cell and the second cell is a low power (LP) cell; or

the first cell is an LP cell and the second cell is an HP cell.

13. The method of claim 11 , wherein the populating further includes:

within at least one of the one or more combination rows and relative the second direction:

stacking a third instance of the first cell on a third instance of the second cell resulting in a 1st cell/2nd cell stack; and

configuring the 1st cell/2nd cell stack as an integral cell; or

within at least one of the one or more combination rows and relative the second direction:

stacking a fourth instance of the second cell on a fourth instance of the first cell resulting in a 2nd cell/1st cell stack; and

configuring the 2nd cell/1st cell stack as an integral cell.

14. The method of claim 13 , wherein the generating the layout diagram further includes:

configuring one or more rows as first-cell-only rows, the first-cell-only configuring including:

relative to the second direction, setting a height of each of the one or more first-cell-only rows to be substantially equal to the first height of the first cell;

relative to the second direction, interspersing the one or more first-cell-only rows among the one or more combination rows; and

populating each of the one or more first-cell-only rows including:

within each of the one or more first-cell-only rows, inserting another instance of the first cell.

15. A semiconductor device comprising:

cell regions arranged in rows which extend substantially in a first direction, the rows including a first row and a second row,

the second row being adjacent to the first row in a second direction substantially perpendicular to the first direction; and

the second row being a combination row having:

relative to the second direction, a height substantially equal to a sum of a first height of a first cell region and a second height of a second cell region, the first cell region being different than the second cell region, and the first height being different than the second height;

relative to the second direction, a first instance of the first cell region stacked on a first instance of the second cell region such that the first instance of the first cell region is between the first row and the first instance of the second cell region; and

relative to the second direction, a second instance of the second cell region stacked on a second instance of the first cell region such that the second instance of the second cell region is between the first row and the second instance of the first cell region.

16. The semiconductor device of claim 15 , wherein:

the first cell region is a high power (HP) cell region and the second cell region is a low power (LP) cell region; or

the first cell region is an LP cell region and the second cell region is an HP cell region.

17. The semiconductor device of claim 15 , wherein the rows further include one or more additional combination rows including:

relative the second direction, a third instance of the first cell region stacked on a third instance of the second cell region which represents a 1st cell/2nd cell stack, and wherein the 1st cell/2nd cell stack is configured as an integral cell region; and

relative the second direction, a fourth instance of the second cell region stacked on a fourth instance of the first cell region which represents a 2nd cell/1st cell stack, and wherein the 2nd cell/1st cell stack is configured as an integral cell region.

18. The semiconductor device of claim 15 , wherein:

one or more rows are configured as first-cell-region only rows, each first-cell-region-only row having:

relative to the second direction, a height substantially equal to the first height of the first cell region;

the one or more first-cell-region-only rows being interspersed among the one or more combination rows; and

each of the one or more first-cell-region-only rows including at least another instance of the first cell.

19. The semiconductor device of claim 18 , wherein:

one or more rows are configured as second-cell-region-only rows, each second-cell-region-only row having:

relative to the second direction, a height substantially equal to the second height of the second cell region;

the one or more second-cell-region-only rows being interspersed among the one or more combination rows and among the one or more first-cell-region-only rows; and

each of the one or more second-cell-region-only rows including at least another instance of the second cell region.

20. The semiconductor device of claim 15 , wherein:

one or more rows are configured as second-cell-region-only rows, each second-cell-region-only row having:

relative to the second direction, a height substantially equal to the second height of the second cell region;

the one or more second-cell-region-only rows being interspersed among the one or more combination rows; and

each of the one or more second-cell-region-only rows including at least another instance of the second cell region.