Page buffer circuit, semiconductor memory apparatus including page buffer circuit, and operating method of semiconductor memory apparatus
A page buffer circuit includes a sensing latch circuit and a caching latch circuit. The sensing latch circuit is configured to receive and sense data that is stored in a memory cell during a normal read operation. The caching latch circuit is configured to receive and sense the data that is stored in the memory cell during a suspend read operation.
1. A page buffer circuit comprising:
a sensing latch circuit configured to receive and sense data that is stored in a memory cell during a normal read operation; and
a caching latch circuit configured to receive data that is stored in the sensing latch circuit and output the received data as final data during the normal read operation and configured to receive and sense the data that is stored in the memory cell and output the sensed data as the final data during a suspend read operation,
wherein, during the suspend read operation, the sensing latch circuit stores verification data for a program operation.
2. The page buffer circuit according to claim 1 , wherein, during the normal read operation, the sensing latch circuit is configured to store data that is currently being sensed, and the caching latch circuit is configured to store previous data that is sensed before the data is sensed by the sensing latch circuit.
3. The page buffer circuit according to claim 1 , further comprising:
a plurality of data latch circuits configured to store verification data during the program operation.
4. The page buffer circuit according to claim 1 , wherein the sensing latch circuit performs a verification operation during the program operation.
5. The page buffer circuit according to claim 1 , further comprising:
a data transfer circuit configured to transfer, to a sensing node, the data that is stored in the memory cell, during the normal read operation and the suspend read operation.
6. A semiconductor memory apparatus comprising:
a memory device, including a plurality of page buffer circuits, configured to store data; and
a memory control device configured to generate a command signal that corresponds to a suspend read operation, based on request information that corresponds to the suspend read operation during a program operation on the memory device and configured to control the memory device based on the command signal,
wherein each of the plurality of page buffer circuits comprises:
a sensing latch circuit configured to receive and sense data that is stored in a memory cell during a normal read operation; and
a caching latch circuit configured to receive data that is stored in the sensing latch circuit and output the received data as final data during the normal read operation and configured to receive and sense the data that is stored in the memory cell and output the sensed data as the final data during the suspend read operation.
7. The semiconductor memory apparatus according to claim 6 , wherein the memory control device is configured to generate the command signal that corresponds to the normal read operation or the suspend read operation for the memory device and configured to provide the generated command signal to the memory device.
8. The semiconductor memory apparatus according to claim 6 , wherein the memory control device comprises:
a request transmission circuit configured to receive the request information that corresponds to the suspend read operation during the program operation on the memory device; and
a command control circuit configured to generate the command signal that corresponds to the suspend read operation based on an output signal of the request transmission circuit.
9. The semiconductor memory apparatus according to claim 8 , wherein the request transmission circuit is configured to compare a latency value that corresponds to an operation that is being performed by the memory device with a latency value that corresponds to the suspend read operation and configured to provide a comparison result to the command control circuit.
10. The semiconductor memory apparatus according to claim 8 , wherein the memory control device further comprises a data control circuit configured to receive data that corresponds to the suspend read operation from the memory device during the suspend read operation.
11. The semiconductor memory apparatus according to claim 6 , wherein the memory device comprises:
a memory cell array circuit configured to store the data;
an operation driving circuit configured to drive the plurality of page buffer circuits that are connected to the memory cell array circuit; and
an operation control circuit configured to control the operation driving circuit during the normal read operation and the suspend read operation.
12. The semiconductor memory apparatus according to claim 6 , wherein, during the normal read operation, the sensing latch circuit is configured to store data that is currently being sensed, and the caching latch circuit is configured to store previous data that is sensed before the data is sensed by the sensing latch circuit.
13. The semiconductor memory apparatus according to claim 6 , wherein each of the plurality of page buffer circuits further comprises:
a plurality of data latch circuits configured to store verification data during the program operation.
14. The semiconductor memory apparatus according to claim 6 , wherein the sensing latch circuit is configured to perform a verification operation during the program operation.
15. The semiconductor memory apparatus according to claim 6 , wherein each of the plurality of page buffer circuits further comprises:
a data transfer circuit configured to transfer the data that is stored in the memory cell to a sensing node during the normal read operation and the suspend read operation.
16. An operating method of a semiconductor memory apparatus, the operating method comprising:
performing, through a memory device, a program operation;
requesting the memory device to perform a suspend read operation;
transferring data that is stored in a memory cell to a sensing node;
sensing, through a caching latch circuit, the data that is transferred to the sensing node; and
outputting data that corresponds to the suspend read operation,
wherein, during the suspend read operation, a sensing latch circuit stores verification data for the program operation.
17. The operating method according to claim 16 , wherein, during a normal read operation, the caching latch circuit is configured to receive data that is stored in the sensing latch circuit and configured to output the received data as final data.
18. The operating method according to claim 17 , wherein the performing of the program operation includes the sensing latch circuit storing the verification data.
19. The operating method according to claim 16 , wherein the performing of the program operation includes a plurality of data latch circuits storing a plurality of verification data.