Semiconductor die with stepped side surface

1. A semiconductor device comprising:

a substrate;

a semiconductor die including an active surface with bond pads, an opposite inactive surface, and stepped side surfaces extending between the active surface and the opposite inactive surface;

wherein a surface area of the active surface is smaller than a surface area of the opposite inactive surface;

wherein the stepped side surfaces include a first planar surface extending from the opposite inactive surface towards the active surface, a second planar surface extending from the active surface towards the opposite inactive surface, and a side surface offset between the first planar surface and the second planar surface;

wherein the second planar surface is offset towards a center of the semiconductor die from the first planar surface such that the side surface offset faces the active surface; and

an adhesive layer covering at least a portion of a surface area of the first planar surface and attaching the semiconductor die to the substrate.

2. The semiconductor device of claim 1 , wherein the first planar surface extends towards the active surface at least 25 percent of a distance separating the active surface from the opposite inactive surface, and

wherein the second planar surface extends towards the opposite inactive surface at least 25 percent of the distance separating the active surface from the opposite inactive surface.

3. The semiconductor device of claim 1 , wherein the first planar surface is offset at least 10 micrometers (μm) from the second planar surface.

4. The semiconductor device of claim 1 , wherein the first planar surface is offset at from 10 to 40 μm from the second planar surface.

5. The semiconductor device of claim 1 ,

wherein a surface area of the opposite inactive surface is smaller than a surface area of the active surface, and

wherein the second planar surface is offset away from a center of the semiconductor die from the first planar surface such that the side surface offset faces the opposite inactive surface.

6. The semiconductor device of claim 1 ,

wherein first planar surface is parallel to the second planar surface, and

wherein the side surface offset is perpendicular to the first planar surface and the second planar surface.

7. The semiconductor device of claim 1 , wherein the adhesive layer is a die attach paste.

8. The semiconductor device of claim 7 , wherein the die attach paste includes silver particles.

9. The semiconductor device of claim 1 ,

wherein the adhesive layer forms a fillet covering at least 75 percent of the first planar surface, and

wherein at least 75 percent of the second planar surface is free of the adhesive layer.

10. The semiconductor device of claim 1 , wherein the stepped side surfaces are configured to limit coverage of the stepped side surfaces with the adhesive layer.

11. The semiconductor device of claim 1 , wherein the adhesive layer is adjacent to at least a portion of the side surface offset.

12. The semiconductor device of claim 1 , wherein the substrate is a metallic pad.

13. The semiconductor device of claim 12 , further comprising leads spaced from the metallic pad by a gap.

14. The semiconductor device of claim 13 , further comprising wire bonds extending between the bond pads of the semiconductor die and the leads.

15. The semiconductor device of claim 1 , further comprising mold compound covering the semiconductor die, the adhesive layer, and at least partially covering the substrate.

16. The semiconductor device of claim 1 , wherein the adhesive layer covers all of the surface area of the first planar surface.

17. The semiconductor device of claim 16 wherein the adhesive layer further covers a portion, but not all, of the first planar surface.

18. A semiconductor die comprising:

an active surface with bond pads;

an opposite inactive surface;

stepped side surfaces extending between the active surface and the opposite inactive surface;

wherein the stepped side surfaces include a first planar surface extending from the opposite inactive surface towards the active surface, a second planar surface extending from the active surface towards the opposite inactive surface, and a side surface offset between the first planar surface and the second planar surface;

wherein a surface area of the active surface is smaller than a surface area of the opposite inactive surface; and

wherein the second planar surface is offset towards a center of the die from the first planar surface such that the side surface offset faces the active surface.

19. The semiconductor die of claim 18 ,

wherein the first planar surface extends towards the active surface at least 25 percent of a distance separating the active surface from the opposite inactive surface, and

wherein the second planar surface extends towards the opposite inactive surface at least 25 percent of the distance separating the active surface from the opposite inactive surface.

20. The semiconductor die of claim 18 , wherein the first planar surface is offset at least 10 micrometers (μm) from the second planar surface.

21. The semiconductor die of claim 18 , wherein an adhesive layer covers all of the surface area of the first planar surface.

22. The semiconductor die of claim 21 wherein the adhesive layer further covers a portion, but not all, of the first planar surface.