IP Library › Granted Patent US 12,062,826
Granted Patent B2
US 12,062,826 · App. 17/515,055 · Granted Aug 13, 2024

Superconducting qubit memory of quantum computer

Inventors: Jaehyeong Lee (Gwacheon-si, KR); Hyeokshin Kwon (Seoul, KR); Jaeho Shin (Cheonan-si, KR); Taehwan Jang (Suwon-si, KR); Insu Jeon (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01P3/003G06N10/00H01P7/086
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Quick Facts
Patent No.
US 12,062,826
App. No.
17/515,055
Granted
Aug 13, 2024
Kind
B2
Abstract

A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.

Claims (24)

1. A qubit memory of a quantum computer, the qubit memory comprising:

a first readout unit;

a first transmon; and

a first data storage unit configured to store quantum information,

wherein the first data storage unit comprises:

a substrate; and

a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on the substrate, and

wherein the insulating layer is separated from the substrate and is configured to cover an entire upper surface of the first superconducting waveguide layer.

2. The qubit memory of claim 1 , wherein the first superconducting waveguide layer comprises a superconducting resonator.

3. The qubit memory of claim 1 , wherein the first superconducting waveguide layer has a thickness in a range from about 50 nm to about 100 nm.

4. The qubit memory of claim 1 , wherein the superconductor layer has a thickness in a range from about 50 nm to about 100 nm.

5. The qubit memory of claim 1 , wherein the insulating layer continuously extends onto the superconductor layer and covers an entire upper surface of the superconductor layer.

6. The qubit memory of claim 5 ,

wherein the first superconducting waveguide layer, the insulating layer, and the superconductor layer constitute a first stack structure of a plurality of stack structures, and

wherein the plurality of stack structures are sequentially stacked on the substrate.

7. The qubit memory of claim 6 , wherein each of the plurality of stack structures comprises a respective first superconducting waveguide layer, a respective insulating layer, and a respective superconductor layer.

8. The qubit memory of claim 7 , wherein some stack structures from among the plurality of stack structures have a first buried shape of the superconductor layer in the insulating layer,

wherein the remaining stack structures from among the plurality of stack structures have a second buried shape of the superconductor layer in the insulating layer, and

wherein the second buried shape is different from the first buried shape.

9. The qubit memory of claim 6 , further comprising:

a second readout unit;

a second transmon; and

a second data storage unit configured to store quantum information,

wherein the second data storage unit comprises a second plurality of stack structures that are the same as the plurality of stack structures.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2021
From: LEE, JAEHYEONG; KWON, HYEOKSHIN; SHIN, JAEHO; JANG, TAEHWAN; JEON, INSU
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 057976/0623 →
Priority Claims (1)
KR 10-2020-0150514 · Nov 11, 2020 · national
Continuity (1)
Related Publication 20220149501A1 · May 12, 2022