Three-dimensional memory device and manufacturing method thereof
A memory device includes a first stacking structure, a second stacking structure, a plurality of first isolation structures, gate dielectric layers, channel layers and channel layers. The first stacking structure includes a plurality of first gate layers, and a second stacking structure includes a plurality of second gate layers, where the first stacking structure and the second stacking structure are located on a substrate and separated from each other through a trench. The first isolation structures are located in the trench, where a plurality of cell regions are respectively confined between two adjacent first isolation structures of the first isolation structures in the trench, where the first isolation structures each includes a first main layer and a first liner surrounding the first main layer, where the first liner separates the first main layer from the first stacking structure and the second stacking structure. The gate dielectric layers are respectively located in one of the cell regions, and cover opposing sidewalls of the first stacking structure and the second stacking structure as well as opposing sidewalls of the first isolation structures. The channel layers respectively cover an inner surface of one of the gate dielectric layers. The conductive pillars stand on the substrate within the cell regions, and are laterally surrounded by the channel layers, where at least two of the conductive pillars are located in each of the cell regions, and the at least two conductive pillars in each of the cell regions are laterally separated from one another.
1. A method of manufacturing a memory device, comprising:
forming a multilayer stack comprising insulating layers and sacrificial layers arranged in alternation;
forming trenches in the multilayer stack;
replacing the sacrificial layers with gate layers;
forming dummy dielectric structures in the trenches to form cell regions separated from one another;
forming memory films on sidewalls of the cell regions;
forming channel layers on the memory films;
forming conductive structures to fill up the cell regions;
patterning the conductive structures to form at least two conductive pillars in each of the cell regions;
removing the dummy dielectric structures; and
forming first isolation structures between the at least two conductive pillars in each of the cell regions and forming second isolation structures between the cell regions, wherein forming the first isolation structures comprises:
forming first liners on opposite sidewalls of the at least two of the conductive pillars and opposite sidewalls of a respective one of the channel layers exposed by the at least two of the conductive pillars in each of the cell regions by ALD; and
filling up the cell regions with a first dielectric material to form the first isolation structures respectively surrounded by the first liners.
2. The method of claim 1 , wherein forming the second isolation structures comprises:
forming, on opposite sidewalls of two adjacent cell regions in each of the trenches and the opposite sidewalls of each of the trenches exposed by the two adjacent cell regions, second liners by ALD; and
filling up gaps respectively sandwiched between the two adjacent cell regions in each of the trenches with a second dielectric material to form the second isolation structures surrounded by the second liners.
3. The method of claim 1 , prior to forming the dummy dielectric structures in the trenches and after replacing the sacrificial layers with the gate layers, further comprising:
laterally recessing the gate layers in respect to the insulating layers.
4. The method of claim 1 , wherein forming the dummy dielectric structures in the trenches to form the cell regions separated from one another comprises:
forming a dummy dielectric material in the trenches; and
removing portions of the dummy dielectric material to form the dummy dielectric structures separating the cell regions separated from one another.
5. The method of claim 1 , wherein forming the memory films on sidewalls of the cell regions comprises:
conformally forming the memory films on the cell regions to respectively cover all sidewalls and bottom surface of each of the cell regions.
6. The method of claim 1 , wherein forming the memory films on sidewalls of the cell regions comprises:
selectively forming the memory films on the cell regions to respectively cover sidewalls of each of the cell regions located at the multilayer stack.
7. A method of manufacturing a memory device, comprising:
forming a multilayer stack comprising insulating layers and sacrificial layers arranged in alternation along a vertical direction over a substrate;
patterning the multilayer stack into a plurality of stacking structures being separated from each other and standing over the substrate;
replacing, in the plurality of stacking structures, the sacrificial layers with gate layers;
disposing dummy dielectric structures next to the plurality of stacking structures over the substrate, the dummy dielectric structures propping again sidewalls of the plurality of stacking structures, the plurality of stacking structures being arranged along a first horizontal direction, the dummy dielectric structure arranged along a second horizontal direction, wherein a cell regions is confined by two adjacent of the plurality of stacking structures and two adjacent of the dummy dielectric structures;
sequentially forming memory films, channel layers and conductive structures in the cell regions to fill the cell regions;
patterning the conductive structures to form at least two conductive pillars in each of the cell regions separating from each other by a first recess;
removing the dummy dielectric structures to form second recesses;
forming first isolation structures in the first recesses included in the cell regions, comprising:
forming first liners to line sidewalls of the first recesses by ALD; and
filling the first recesses with a first dielectric material to form the first isolation structures respectively surrounded by the first liners; and
forming second isolation structures in the second recesses, comprising:
forming second liners to line sidewalls of the second recesses by ALD; and
filling the second recesses with a second dielectric material to form the second isolation structures respectively surrounded by the second liners.
8. The method of claim 7 , wherein in a horizontal cross-section of the memory device, shapes of the cell regions is formed to be circular, oval or elliptical, wherein for each of the cell regions:
a shape of the memory film is formed to include a circular annulus frame, an oval annulus frame, or an elliptical annulus frame;
a shape of the channel layer is formed to include a circular annulus frame, an oval annulus frame, or an elliptical annulus frame; and
shapes of the at least two conductive pillars are formed to include circular shapes, oval shapes or elliptical shapes.
9. The method of claim 7 , wherein in a horizontal cross-section of the memory device, shapes of the cell regions is formed to be quadrilateral, wherein for each of the cell regions:
a shape of the memory film is formed to include a strip shape;
a shape of the channel layer is formed to include an annulus frame having an outer sidewall of a quadrilateral shape and an inner sidewall of a circular, oval or elliptical shape; and
shapes of the at least two conductive pillars are formed to include circular shapes, oval shapes or elliptical shapes.
10. The method of claim 7 , wherein in a horizontal cross-section of the memory device, shapes of the cell regions is formed to be quadrilateral, wherein for each of the cell regions:
a shape of the memory film is formed to include a strip shape;
a shape of the channel layer is formed to include a strip shape; and
shapes of the at least two conductive pillars are formed to include truncated-circular shapes, truncate-oval shapes or truncated-elliptical shapes.
11. The method of claim 7 , wherein in a horizontal cross-section of the memory device, for each of the cell regions:
a first width of the first isolation structure at a center of a respective cell region is less than a second width of the first isolation structure at edges of the respective cell region, where the first width and the second width are measured along the second horizontal direction.
12. The method of claim 7 , wherein in a horizontal cross-section of the memory device, for each of the second recesses:
a third width of the second isolation structure at a center of a respective second recess is less than a fourth width of the first isolation structure at edges of the second recess, where the third width and the fourth width are measured along the second horizontal direction.
13. The method of claim 7 , wherein disposing the dummy dielectric structures next to the plurality of stacking structures over the substrate comprises:
forming a dummy dielectric material between every two adjacent of the plurality of stacking structure over the substrate; and
removing portions of the dummy dielectric material to form the dummy dielectric structures being disposed next to the plurality of stacking structures over the substrate.
14. A method of manufacturing a memory device, comprising:
forming a plurality of stacking structures being separated from each other and standing over a substrate, the plurality of stacking structures each comprising dielectric layers and gate layers arranged in alternation;
laterally recessing portions of the gate layers in respect to the dielectric layers to form a plurality of lateral recesses;
disposing dummy dielectric structures next to the plurality of stacking structures over the substrate to form cell regions each being confined by two adjacent of the plurality of stacking structures and two adjacent of the dummy dielectric structures;
sequentially forming memory films, channel layers and conductive structures in the cell regions and a part of the lateral recess;
patterning the conductive structures to form at least two conductive pillars in each of the cell regions separating from each other by a first recess; and
forming first isolation structures in the first recesses included in the cell regions and the lateral recess, comprising:
forming first liners to line sidewalls of the first recesses and the lateral recesses by ALD; and
filling the first recesses with a first dielectric material to form the first isolation structures respectively surrounded by the first liners.
15. The method of claim 14 , further comprising:
removing the dummy dielectric structures to form second recesses prior to forming the first isolation structures; and
forming second isolation structures in the second recesses and the lateral recess, comprising:
forming second liners to line sidewalls of the second recesses and the lateral recesses by ALD; and
filling the second recesses with a second dielectric material to form the second isolation structures respectively surrounded by the second liners.
16. The method of claim 15 , wherein forming the first isolation structures and the forming the second isolation structure are simultaneously performed in a same step.
17. The method of claim 14 , wherein in a horizontal cross-section of the memory device, shapes of the cell regions is formed to be circular, oval or elliptical, wherein for each of the cell regions:
a shape of the memory film is formed to include a circular annulus frame, an oval annulus frame, or an elliptical annulus frame;
a shape of the channel layer is formed to include a circular annulus frame, an oval annulus frame, or an elliptical annulus frame; and
shapes of the at least two conductive pillars are formed to include circular shapes, oval shapes or elliptical shapes.
18. The method of claim 14 , wherein in a horizontal cross-section of the memory device, shapes of the cell regions is formed to be quadrilateral, wherein for each of the cell regions:
a shape of the memory film is formed to include a strip shape;
a shape of the channel layer is formed to include an annulus frame having an outer sidewall of a quadrilateral shape and an inner sidewall of a circular, oval or elliptical shape; and
shapes of the at least two conductive pillars are formed to include circular shapes, oval shapes or elliptical shapes.
19. The method of claim 14 , wherein in a horizontal cross-section of the memory device, shapes of the cell regions is formed to be quadrilateral, wherein for each of the cell regions:
a shape of the memory film is formed to include a strip shape;
a shape of the channel layer is formed to include a strip shape; and
shapes of the at least two conductive pillars are formed to include truncated-circular shapes, truncate-oval shapes or truncated-elliptical shapes.
20. The method of claim 14 , wherein disposing dummy dielectric structures next to the plurality of stacking structures over the substrate comprises:
forming a dummy dielectric material between every two adjacent of the plurality of stacking structure over the substrate; and
removing portions of the dummy dielectric material to form the dummy dielectric structures being disposed next to the plurality of stacking structures over the substrate.