Apparatus for treating neurological disorders by electrostimulation and method for processing neural signals collected by the said apparatus
Apparatuses and methods for treating neurological disorders by electro-stimulation. The apparatus may include a neural input signal acquisition module having a front-end block configured to amplify the potential difference of its input signals (V 1a , V 2a ) and to filter a stimulus artifact and may include a multi-stage fully-differential switched capacitor circuit (e.g., an integrated circuit) configured for discrete-time signal processing.
1. A neural input signal acquisition module comprising:
a front-end block configured to amplify differences between neural input signals (V 1a , V 2a ) received by the acquisition module and to filter out frequencies above a predefined frequency band to suppress stimulation artifacts in the neural input signals,
wherein the front-end block comprises a multi-stage fully-differential switched capacitor circuit configured for discrete-time signal processing.
2. The apparatus of claim 1 , wherein the front-end block comprises a pre-filter stage and a suppression filter stage positioned downstream from the pre-filter stage.
3. The apparatus of claim 2 , wherein each of the pre-filter stage and the suppression filter stage comprises a fully-differential switched capacitor circuit configured for discrete-time signal processing.
4. The apparatus of claim 3 , wherein the pre-filter stage comprises a first fully-differential low-pass switched capacitor filter, clocked at a first clock frequency.
5. The apparatus of claim 4 , wherein the suppression filter stage comprises a second fully-differential low-pass switched capacitor filter, clocked at a second clock frequency.
6. The apparatus of claim 5 , wherein the first fully-differential switched capacitor filter of the pre-filter stage has an order lower than an order of the second fully-differential switched capacitor filter of the suppression filter stage.
7. The apparatus of claim 5 , wherein the first clock frequency of the first fully-differential switched capacitor filter of the pre-filter stage is greater than the second clock frequency of the second fully-differential switched capacitor filter of the suppression filter stage.
8. The apparatus of claim 5 , wherein a first cut-off frequency of the first fully-differential switched capacitor filter of the pre-filter stage is greater than a second cut-off frequency of the second fully-differential switched capacitor filter of the suppression filter stage.
9. The apparatus of claim 5 , wherein a first cut-off frequency of the first fully-differential switched capacitor filter of the pre-filter stage is at least 50 Hz and is lower than the second clock frequency.
10. The apparatus of claim 5 , wherein a second cut-off frequency of the second fully-differential switched capacitor filter of the suppression filter stage is in a range of about 35-2000 Hz.
11. The apparatus of claim 4 , wherein the first clock frequency is at least 1 KHz.
12. The apparatus of claim 3 , wherein the fully-differential switched capacitor circuit comprises at least one bilinear switched capacitor integrator.
13. The apparatus of claim 12 , wherein the at least one bilinear switched capacitor integrator is configured to implement correlated double sampling.
14. The apparatus of claim 12 , wherein the at least one bilinear switched capacitor integrator comprises two inputs configured to receive, respectively, the neural input signals (V 1a , V 2a ), and the two inputs are alternatively connectable to one end of two input capacitors (C 1 , C 2 ), the other end of the two input capacitors (C 1 , C 2 ) being configured to alternatively connect to a reference voltage source (V ref ) or, each respectively, to one of two inputs of an operational amplifier.
15. The apparatus of claim 14 , wherein each input of the operational amplifier is connectable to one respective output of the operational amplifier through interposition of a first (C 3 , C 5 ) and a second (C 4 , C 6 ) pair of feedback capacitors, respectively.
16. The apparatus of claim 15 , wherein the feedback capacitor pairs (C 3 , C 5 ) and (C 4 , C 6 ) comprise each a first (C 3 , C 4 ) and a second (C 5 , C 6 ) feedback capacitors connected in parallel, and are configured to alternatively connect to the respective input of the operational amplifier.
17. The apparatus of claim 12 , wherein the at least one bilinear switched capacitor integrator comprises two inputs configured to receive, respectively, the neural input signals (V 1a , V 2a ) which are alternatively connectable to one end of two input capacitors (C 1 , C 2 ), the other end of the two input capacitors (C 1 , C 2 ) being configured to alternatively connect to a reference voltage source (V ref ) or, each respectively, to one of two inputs of an operational amplifier, each input of the operational amplifier being connectable to one respective output of the operational amplifier through interposition of a first (C 3 ) and a second (C 4 ) feedback capacitor, respectively.
18. The apparatus of claim 3 , wherein the fully-differential switched capacitor circuit of the pre-filter stage and/or of the suppression filter stage is implemented as ladder filter comprising a plurality of switched capacitor integrators in an active emulation of lossless LC ladder structure.
19. The apparatus of claim 1 , wherein the acquisition module further comprises an A/D converter block connected downstream from the front-end block.
20. The apparatus of claim 19 , wherein the A/D converter block optionally comprises a delta-sigma converter.
21. The apparatus of claim 19 , wherein the A/D converter block comprises a fully-differential switched-capacitor circuit.
22. The apparatus of claim 19 , wherein the A/D converter block comprises a first sampling stage, followed by a filter stage configured to remove a quantization noise and a decimation stage.
23. The apparatus of claim 1 , wherein the acquisition module further comprises one or more functional modules selected from:
a first functional module configured to receive an input synchronization signal coming from the stimulation module for disconnecting or grounding the inputs of the front-end block during stimulus pulses generated by the stimulation module, the first functional module being connected upstream from the front-end block;
a second functional module configured to receive high frequencies in a signal produced by the operation of the first functional module; and/or
a third functional module configured to provide high-pass filtering so as to mitigate offset potentials at the at least one implantable electrode.
24. The apparatus of claim 1 , wherein the acquisition module comprises an FPGA and/or an ASIC.
25. A neural input signal acquisition module comprising:
a front-end block comprising:
a pre-filter stage configured to amplify differences between neural input signals (V 1a , V 2a ); and
a suppression filter stage configured to filter out frequencies above a predefined frequency band to suppress stimulation artifacts in the neural input signals,
wherein the suppression filter stage is positioned downstream from the pre-filter stage, and each of the pre-filter stage and the suppression filter stage comprises a fully-differential switched capacitor circuit configured for discrete-time signal processing.