IP Library › Granted Patent US 12,068,203
Granted Patent B2
US 12,068,203 · App. 17/511,231 · Granted Aug 20, 2024

Method for manufacturing semiconductor device structure

Inventor: Hsih-Yang Chiu (Taoyuan, TW)
Assignee: NANYA TECHNOLOGY CORPORATION
H01L21/823481H01L21/761H01L21/823475H01L24/80H01L2224/80895H01L2224/80896
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Quick Facts
Patent No.
US 12,068,203
App. No.
17/511,231
Granted
Aug 20, 2024
Kind
B2
Abstract

A method for manufacturing a semiconductor device structure including a doped region under an isolation feature. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate comprises a first well region with a first conductive type; forming an isolation feature extending from the second surface of the substrate; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region under the isolation feature, wherein the first doped region has a second conductive type different from the first conductive type; and providing a circuit structure on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled with the first doped region.

Claims (12)

1. A method of manufacturing a semiconductor device structure, comprising:

providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate comprises a first well region with a first conductive type;

forming an isolation feature extending from the second surface of the substrate;

forming a first transistor and a second transistor adjacent to the second surface of the substrate;

forming a first doped region under the isolation feature, wherein the first doped region has a second conductive type different from the first conductive type;

providing a circuit structure on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled with the first doped region;

forming a first conductive feature extending between the first surface of the substrate and the first doped region, wherein the first conductive feature electrically couples with the circuit structure;

forming a second well region in the substrate and surrounding the first doped region; and

forming a third well region spaced apart from the second surface of the substrate and in contact with the second well region.

2. The method of claim 1 , further comprising:

forming a second doped region in the third well region; and

forming a second conductive feature extending between the first surface of the substrate and the second doped region.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2021
From: CHIU, HSIH-YANG
To: NANYA TECHNOLOGY CORPORATION
Reel/Frame 057920/0267 →
Continuity (1)
Related Publication 20230126134A1 · Apr 27, 2023
Cited By (1)
US 12,191,303