Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region;
forming a HV device on the HV region, wherein the HV device comprises:
a first base on the substrate;
a first gate dielectric layer on the first base; and
a first gate electrode on the first gate dielectric layer;
forming a LV device on the LV region, wherein the LV device comprises:
a fin-shaped structure on the substrate; and
a second gate electrode on the fin-shaped structure, wherein a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.
2. The method of claim 1 , wherein a top surface of the first gate electrode is even with a top surface of the second gate electrode.
3. The method of claim 1 , further comprising:
forming the first base on the HV region, a second base on the MV region, and the fin-shaped structure on the LV region;
forming an insulating layer around the first base, the second base, and the fin-shaped structure;
removing part of the first base;
forming the first gate dielectric layer on the first base;
forming a second gate dielectric layer on the second base;
removing the insulating layer to form a shallow trench isolation (STI);
forming a third gate dielectric layer on the fin-shaped structure;
forming the first gate electrode on the first gate dielectric layer, the second gate electrode on the third gate dielectric layer, and a third gate electrode on the second gate dielectric layer;
forming a first source/drain region adjacent to the first gate electrode; and
forming a second source/drain region adjacent to the second electrode.
4. The method of claim 3 , wherein a top surface of the first gate dielectric layer is lower than a top surface of the second gate dielectric layer.
5. The method of claim 3 , wherein a top surface of the first gate electrode is even with a top surface of the third gate electrode.
6. The method of claim 3 , wherein a top surface of the first source/drain region is even with the top surface of the fin-shaped structure.
7. The method of claim 3 , further comprising forming an electrostatic discharge (ESD) protection ring around the HV device.
8. The method of claim 7 , wherein a top surface of the ESD protection ring is even with the top surface of the first source/drain region.
9. A semiconductor device, comprising:
a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region;
a HV device on the HV region, wherein the HV device comprises:
a first base on the substrate;
a first gate dielectric layer on the first base;
a first gate electrode on the first gate dielectric layer;
a LV device on the LV region, wherein the LV device comprises:
a fin-shaped structure on the substrate;
a second gate electrode on the fin-shaped structure, wherein a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.
10. The semiconductor device of claim 9 , wherein a top surface of the first gate electrode is even with a top surface of the second gate electrode.
11. The semiconductor device of claim 9 , wherein the HV device comprises a source/drain region adjacent to the first gate electrode, wherein a top surface of the source/drain region is even with the top surface of the fin-shaped structure.
12. The semiconductor device of claim 11 , further comprising a shallow trench isolation (STI) between the first base and the source/drain region.
13. The semiconductor device of claim 11 , further comprising an electrostatic discharge (ESD) protection ring around the HV device.
14. The semiconductor device of claim 13 , wherein a top surface of the ESD protection ring is even with the top surface of the source/drain region.
15. The semiconductor device of claim 9 , further comprising a MV device on the MV region, wherein the MV device comprises:
a second base on the substrate;
a second gate dielectric layer on the second base; and
a third gate electrode on the second gate dielectric layer.
16. The semiconductor device of claim 15 , wherein a top surface of the first gate dielectric layer is lower than the top surface of the second gate dielectric layer.
17. The semiconductor device of claim 15 , wherein a top surface of the first gate electrode is even with a top surface of the third gate electrode.