IP Library › Granted Patent US 12,068,720
Granted Patent B2
US 12,068,720 · App. 17/351,560 · Granted Aug 20, 2024

Barely Doherty dual envelope tracking (BD2E) circuit

Inventor: Nadim Khlat (Cugnaux, FR)
Assignee: Qorvo US, Inc.
H03F1/0288H03F3/245H04B1/04H03F2200/105H03F2200/451H04B2001/045
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,068,720
App. No.
17/351,560
Granted
Aug 20, 2024
Kind
B2
Abstract

A barely Doherty dual envelope tracking (BD 2 E) circuit has a transmitter chain that includes an envelope tracking (ET) circuit that controls a Doherty dual power amplifier array. The ET circuit provides two control signals (supply voltage signals) that are used to control or modulate a carrier amplifier and a peaking amplifier independently of one another. The BD 2 E circuit includes an improved impedance inverter that isolates the peaking amplifier from the carrier amplifier to allow this independent control. By providing independent control, greater linearity may be provided while preserving the efficiency of the circuit.

Claims (60)

1. A power amplifier circuit comprising:

a carrier amplifier;

a peaking amplifier;

an impedance inverter coupling the carrier amplifier to the peaking amplifier, the impedance inverter comprising a supply voltage input node, wherein a supply voltage received at the supply voltage input node modulates the carrier amplifier;

a transformer circuit coupled to the peaking amplifier, the transformer circuit comprising a second supply voltage input node, wherein a second supply voltage received at the second supply voltage input node modulates the peaking amplifier separately from modulation of the carrier amplifier; and

an output node coupled to the transformer circuit, wherein an amplified signal from the transformer circuit may be output at the output node.

2. The power amplifier circuit of claim 1 , wherein:

the supply voltage comprises a Vcc_carrier signal from an envelope tracking integrated circuit (ETIC);

the second supply voltage comprises a Vcc_peaking signal from the ETIC; and

the power amplifier circuit is configured to operate as a Doherty dual amplifier circuit.

3. The power amplifier circuit of claim 1 , wherein the impedance inverter comprises:

a first inductor pair comprising a first inductor and a second inductor having a first node therebetween, wherein the first inductor and the second inductor are positively coupled; and

a second inductor pair comprising a third inductor and a fourth inductor with a second node therebetween, wherein the third inductor and the fourth inductor are positively coupled;

wherein the first node and the second node are coupled to the supply voltage input node.

4. The power amplifier circuit of claim 3 , further comprising a shunt capacitor coupling the supply voltage input node to ground at radio frequencies, but not at baseband frequencies.

5. The power amplifier circuit of claim 3 , wherein the impedance inverter further comprises a variable capacitor electrically parallel to the first inductor pair.

6. The power amplifier circuit of claim 1 , further comprising a direct current (DC) blocking capacitor positioned between the impedance inverter and the transformer circuit.

7. The power amplifier circuit of claim 1 , wherein the power amplifier circuit comprises a differential power amplifier circuit and the carrier amplifier comprises a positive carrier amplifier and a negative carrier amplifier.

8. The power amplifier circuit of claim 1 , wherein the transformer circuit comprises a primary transformer comprising a first inductor and a second inductor with the second supply voltage input node therebetween.

9. The power amplifier circuit of claim 8 , wherein the transformer circuit further comprises a secondary transformer coupled to the output node.

10. The power amplifier circuit of claim 1 , wherein the impedance inverter comprises a first inductor coupled to a second inductor with the supply voltage input node therebetween, the first inductor negatively coupled to the second inductor.

11. A transmitter circuit comprising:

a transceiver;

an envelope tracking (ET) circuit coupled to the transceiver, wherein the ET circuit is configured to provide a first voltage supply signal and a second voltage supply signal; and

a power amplifier circuit comprising:

a carrier amplifier;

a peaking amplifier;

an impedance inverter coupling the carrier amplifier to the peaking amplifier, the impedance inverter comprising a supply voltage input node coupled to the ET circuit to receive the first voltage supply signal; and

a transformer circuit coupled to the peaking amplifier, the transformer circuit comprising a second supply voltage input node coupled to the ET circuit to receive the second voltage supply signal;

wherein the peaking amplifier is modulated separately from the carrier amplifier; and

an output node coupled to the transformer circuit, wherein an amplified signal from the transformer circuit may be output at the output node.

12. The transmitter circuit of claim 11 , wherein the impedance inverter comprises:

a first inductor pair comprising a first inductor and a second inductor having a first node therebetween, wherein the first inductor and the second inductor are positively coupled; and

a second inductor pair comprising a third inductor and a fourth inductor with a second node therebetween, wherein the third inductor and the fourth inductor are positively coupled;

wherein the first node and the second node are coupled to the supply voltage input node.

13. The transmitter circuit of claim 12 , wherein the impedance inverter further comprises a variable capacitor electrically parallel to the first inductor pair.

14. The transmitter circuit of claim 11 , wherein the power amplifier circuit further comprises a direct current (DC) blocking capacitor positioned between the impedance inverter and the transformer circuit.

15. The transmitter circuit of claim 11 , wherein the power amplifier circuit comprises a differential power amplifier circuit and the carrier amplifier comprises a positive carrier amplifier and a negative carrier amplifier.

16. The transmitter circuit of claim 11 , wherein the transformer circuit comprises a primary transformer comprising a first inductor and a second inductor with the second supply voltage input node therebetween.

17. The transmitter circuit of claim 16 , wherein the transformer circuit further comprises a secondary transformer coupled to the output node.

18. A power amplifier circuit comprising:

a carrier amplifier;

a peaking amplifier;

an impedance inverter coupling the carrier amplifier to the peaking amplifier, the impedance inverter comprising:

a first supply voltage input node, wherein a first supply voltage received at the first supply voltage input node modulates the carrier amplifier; and

a second supply voltage input node, wherein a second supply voltage received at the second supply voltage input node modulates the peaking amplifier;

a transformer circuit coupled to the peaking amplifier; and

an output node coupled to the transformer circuit, wherein an amplified signal from the transformer circuit may be output at the output node.

19. The power amplifier circuit of claim 18 , wherein the impedance inverter comprises:

a first inductor;

a second inductor electrically isolated from the first inductor, the second inductor positively coupled to the first inductor;

a third inductor electrically coupled to the first inductor, the first supply voltage input node between the first inductor and the third inductor; and

a fourth inductor electrically isolated from the third inductor, the fourth inductor positively coupled to the third inductor, the fourth inductor electrically coupled to the second inductor, the second supply voltage input node between the second inductor and the fourth inductor.

20. The power amplifier circuit of claim 19 , further comprising a variable capacitor coupling the first inductor and the second inductor.

21. A power amplifier circuit comprising:

a carrier amplifier;

a peaking amplifier;

an impedance inverter coupling the carrier amplifier to the peaking amplifier, the impedance inverter comprising an inductor pair comprising a first inductor positively coupled to a second inductor, the second inductor in series with the first inductor;

a transformer circuit coupled to the peaking amplifier, the transformer circuit comprising a supply voltage input node, wherein a supply voltage received at the supply voltage input node modulates the peaking amplifier and the carrier amplifier; and

an output node coupled to the transformer circuit, wherein an amplified signal from the transformer circuit may be output at the output node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2021
From: KHLAT, NADIM
To: QORVO US, INC.
Reel/Frame 056585/0175 →
Continuity (2)
Provisional Application 63154030 · Feb 26, 2021
Related Publication 20220278651A1 · Sep 1, 2022