Memory array and methods of forming same

1. A device, comprising:

a semiconductor substrate;

a first word line over the semiconductor substrate, the first word line providing a first gate electrode for a first transistor;

a second word line over the first word line, the second word line being insulated from the first word line by a first dielectric material, the second word line providing a second gate electrode for a second transistor over the first transistor;

a source line intersecting the first word line and the second word line;

a bit line intersecting the first word line and the second word line, the bit line being insulated from the source line by a second dielectric material;

a memory film between the first word line and the source line, the memory film further being disposed between the first word line and the bit line, wherein the memory film further extends directly under the bit line; and

a first semiconductor material between the memory film and the source line, the first semiconductor material further being disposed between the first word line and the source line, wherein the first semiconductor material further extends directly under the bit line.

2. The device of claim 1 , wherein the source line provides a first source/drain region for the first transistor and a second source/drain region for the second transistor, and wherein the bit line provides a third source/drain region for the first transistor and a fourth source/drain region for the second transistor.

3. The device of claim 1 , further comprising:

an additional source line intersecting the first word line and the second word line, wherein the additional source line provides a fifth source/drain region for a third transistor; and

an additional bit line intersecting the first word line and the second word line, wherein the additional bit line provides a sixth source/drain region for the third transistor, and wherein the first word line provides a third gate electrode for the third transistor.

4. The device of claim 3 , further comprising a second semiconductor material between the first word line and the additional source line, wherein the second semiconductor material is insulated from the first semiconductor material by a third dielectric material.

5. The device of claim 4 , wherein the memory film is further disposed between the first word line and the second semiconductor material, and wherein the memory film extends continuously from the first semiconductor material to the second semiconductor material.

6. The device of claim 1 , wherein the memory film is a ferroelectric material.

7. The device of claim 1 , wherein the first word line is longer than the second word line.

8. A device, comprising:

a semiconductor substrate;

a first memory cell over the semiconductor substrate, the first memory cell comprising a first thin film transistor, wherein the first thin film transistor comprises:

a gate electrode comprising a portion of a first word line, wherein the first word line extends in a direction parallel to a top surface of the semiconductor substrate;

a first portion of a ferroelectric material, the first portion of the ferroelectric material being on a sidewall of the first word line; and

a first channel region that is part of a semiconductor material, the semiconductor material being on a sidewall of the ferroelectric material;

a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor, and wherein the source line extends in a first direction perpendicular to the top surface of the semiconductor substrate;

a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor, wherein the ferroelectric material and the semiconductor material each extends directly under the bit line, and wherein the bit line extends in a second direction perpendicular to the top surface of the semiconductor substrate; and

a second memory cell over the first memory cell.

9. The device of claim 8 , wherein the second memory cell comprising a second thin film transistor, wherein a second portion of the source line provides a first source/drain electrode for the second thin film transistor, and wherein a second portion of the bit line provides a second source/drain electrode for the second thin film transistor.

10. The device of claim 9 , further comprising a second word line over the first word line, wherein a gate electrode of the second thin film transistor comprises a portion of the second word line, and wherein the first word line is longer than the second word line.

11. The device of claim 8 , wherein the first word line is electrically connected to a second word line disposed above the second memory cell.

12. The device of claim 8 , wherein the first word line is electrically connected to a second word line disposed under the first memory cell.

13. The device of claim 8 , wherein the source line is electrically connected to a conductive routing line disposed above the second memory cell.

14. The device of claim 8 , wherein the source line is electrically connected to a conductive routing line disposed under the first memory cell.

15. A device, comprising:

a first conductive line and a second conductive line over a semiconductor substrate, wherein the second conductive line is disposed over and is separated from the first conductive line by a first insulating material, and wherein the second conductive line is shorter than the first conductive line;

a memory film on sidewalls of the first conductive line and the second conductive line;

a first oxide semiconductor (OS) material on a sidewall of the memory film, wherein the memory film separates the first OS material from the first conductive line and the second conductive line;

a third conductive line on a sidewall of the first OS material;

a fourth conductive line on the sidewall of the first OS material, wherein the first OS material extends continuously from the third conductive line to the fourth conductive line; and

a second insulating material on the sidewall of the first OS material, the second insulating material separating the third conductive line from the fourth conductive line, wherein the second insulating material physically contacts a first sidewall of the third conductive line, and wherein a third insulating material physically contacts a second sidewall of the third conductive line that is opposite to the first sidewall of the third conductive line.

16. The device of claim 15 , further comprising:

a second OS material on the sidewall of the memory film, wherein the memory film separates the second OS material from the first conductive line and the second conductive line; and wherein the third insulating material separates the first OS material from the second OS material.

17. The device of claim 16 , further comprising:

a fifth conductive line on a sidewall of the second OS material, wherein the third insulating material separates the fifth conductive line from the fourth conductive line;

a sixth conductive line on the sidewall of the second OS material, wherein the second OS material extends continuously from the fifth conductive line to the sixth conductive line; and

a fourth insulating material on the sidewall of the second OS material, the fourth insulating material separating the fifth conductive line from the sixth conductive line.

18. The device of claim 15 , wherein the memory film is a ferroelectric material.

19. The device of claim 15 , further comprising:

a first routing line over the second conductive line and electrically connected to the third conductive line; and

a second routing line over the second conductive line and electrically connected to the fourth conductive line.

20. The device of claim 15 , further comprising:

a first routing line over the second conductive line and electrically connected to the first conductive line; and

a second routing line over the second conductive line and electrically connected to the second conductive line.