Synapse array

1. A synapse crossbar array device pre-configured to recognize a pattern, the synapse crossbar array device comprising:

a plurality of Indium-Gallium-Zinc-Oxide (IGZO) thin film transistors (TFTs); and

a plurality of IGZO resistive synapses, each IGZO resistive synapse comprising an IGZO resistive layer, a first electrical contact electrically coupled to one of the plurality of IGZO TFTs and a second electrical contact electrically connected to one of a plurality of column connection lines;

wherein the first electrical contact and the second electrical contact are disposed on the IGZO resistive layer of a corresponding IGZO resistive synapse, and each IGZO resistive synapse having pre-established, factory fabricated dimension and resistivity corresponding to a synapse weight value specific to the pattern such that the synapse crossbar array device is pre-configured to recognize the pattern using the plurality of IGZO resistive synapses,

wherein the synapse weight value is configured to be non-adjustable during a use of the synapse crossbar array device,

wherein the synapse crossbar array device is fully transparent to visible light and is integrated in a display.

2. The synapse crossbar array device of claim 1 , wherein different IGZO resistive synapses have same resistivities with different dimensions.

3. The synapse crossbar array device of claim 1 , wherein different IGZO resistive synapses have same dimensions with different resistivities and are built as programmable resistive memories.

4. The synapse crossbar array device of claim 3 , wherein the different resistivities of the different IGZO resistive synapses are obtained by applying on-chip local specific heating employing one or more voltage sweeps or voltage pulses.

5. The synapse crossbar array device of claim 1 , wherein the IGZO resistive synapses have different dimensions and different resistivities, and are built as partially programmable resistive memories.

6. The synapse crossbar array device of claim 5 , wherein the different resistivities of the different IGZO synapses are obtained by applying on-chip local specific heating employing one or more voltage sweeps or voltage pulses.

7. The synapse crossbar array device of claim 1 , wherein the plurality of column connection lines are arranged in parallel to each other and extended in a first direction.

8. The synapse crossbar array device of claim 1 , wherein each of the plurality of TFTs comprises a gate contact connected to one of a plurality of row connection lines.

9. The synapse crossbar array device of claim 8 , wherein the plurality of the row connection lines are arranged in parallel to each other and extended in a second direction.

10. The synapse crossbar array device of claim 1 , wherein the first and second electrical contacts of each IGZO resistive synapse are made of at least one of Ti/Au, Al, Mo, indium tin oxide (ITO), aluminum zinc oxide (AZO), or any combination thereof.

11. The synapse crossbar array device of claim 1 , wherein each IGZO resistive synapse comprises a dielectric layer disposed between the IGZO layer and a substrate.

12. The synapse crossbar array device of claim 11 , wherein the dielectric layer is made of at least one of SiO2, Al2O3, AlN, or any combination thereof.

13. The synapse crossbar array device of claim 11 , wherein each IGZO resistive synapse is coupled to an adjacent TFT through a substrate and a dielectric layer.

14. The synapse crossbar array device of claim 1 , wherein each IGZO resistive synapse is built as a programmable resistive memory.

15. The synapse crossbar array device of claim 1 , wherein each IGZO resistive synapse is built as a partially programmable resistive memory.