Method of manufacturing a membrane assembly
A method for manufacturing a membrane assembly for EUV lithography, the method including: providing a stack including: at least one membrane layer supported by a planar substrate, wherein the planar substrate has an inner region and a border region around the inner region; and a first sacrificial layer between the planar substrate and the membrane layer; selectively removing the inner region of the planar substrate such that the membrane assembly has: a membrane formed from the at least one membrane layer, and a border holding the membrane, the border having the border region of the planar substrate and the first sacrificial layer situated between the border region and the membrane layer, wherein the selectively removing the inner region of the planar substrate includes using an etchant which has a similar etch rate for the membrane layer and its oxide and a substantially different etch rate for the first sacrificial layer.
1. A membrane assembly for EUV lithography, the membrane assembly comprising:
a membrane formed from at least one membrane layer comprising polycrystalline silicon or monocrystalline silicon; and
a border holding the membrane,
wherein the border is formed from a planar substrate comprising an inner region and a border region around the inner region,
wherein the border resulted from selective removal of the inner region of the planar substrate,
wherein the planar substrate supports the at least one membrane layer and a sacrificial layer such that the border supports the at least one membrane layer and the sacrificial layer, each of the planar substrate, sacrificial layer and at least one membrane layer being of a different material,
wherein the sacrificial layer is between the planar substrate and the at least one membrane layer, and
wherein an etch rate of an etchant of the planar substrate and the at least one membrane layer is different to the etch rate of the etchant of the sacrificial layer and the etch rate of the etchant of the sacrificial layer is at least ten times more than the etch rate of the etchant of the at least one membrane layer.
2. The membrane assembly of claim 1 , wherein the sacrificial layer comprises silicon nitride.
3. The membrane assembly of claim 1 , wherein the planar substrate comprises silicon.
4. The membrane assembly of claim 1 , wherein the planar substrate and the at least one membrane layer comprise silicon.
5. The membrane assembly of claim 1 , wherein the etch rate of the planar substrate is less than the etch rate of the sacrificial layer.
6. The membrane assembly of claim 5 , wherein the etchant comprises phosphoric acid.
7. The membrane assembly of claim 1 , wherein the membrane assembly is for a patterning device or a dynamic gas lock.
8. The membrane assembly of claim 1 , wherein the membrane assembly comprises a ruthenium-based capping layer.
9. The membrane assembly of claim 8 , wherein the ruthenium-based capping layer is arranged on a molybdenum layer.
10. The membrane assembly of claim 9 , wherein the molybdenum layer is arranged on the planar substrate.
11. The membrane assembly of claim 9 , further comprising a Ru/Mo intermixing layer at an interface of the molybdenum layer and the ruthenium-based capping layer.
12. The membrane assembly of claim 11 , further comprising multiple Ru/Mo intermixing layers.
13. A method for manufacturing a membrane assembly for EUV lithography, the method comprising:
providing a stack comprising:
at least one membrane layer supported by a planar substrate, wherein the planar substrate comprises an inner region and a border region around the inner region; and
a sacrificial layer between the planar substrate and the membrane layer, each of the planar substrate, sacrificial layer and at least one membrane layer being of a different material;
selectively removing the inner region of the planar substrate such that the membrane assembly comprises: a membrane formed from the at least one membrane layer, and a border holding the membrane, the border comprising the border region of the planar substrate and the sacrificial layer situated between the border region and the membrane layer,
wherein the selectively removing the inner region of the planar substrate comprises using an etchant which has an etch rate for the membrane layer and its oxide that is different to an etch rate for the sacrificial layer and the etch rate of the etchant of the sacrificial layer is at least ten times more than the etch rate of the etchant of the at least one membrane layer.
14. The method according to claim 13 , further comprising providing a resist on the stack and patterning the resist prior to the selectively removing the inner region.
15. A lithographic apparatus comprising the membrane assembly according to claim 1 .
16. The method according to claim 13 , wherein the etch rate of the planar substrate is less than the etch rate of the sacrificial layer.
17. The method according to claim 13 , wherein the sacrificial layer comprises silicon nitride.
18. The method according to claim 13 , wherein the etchant comprises phosphoric acid.
19. The method according to claim 13 , wherein the membrane assembly comprises a ruthenium-based capping layer.
20. The method according to claim 13 , wherein the membrane assembly is for a patterning device or a dynamic gas lock.