Memory sub-system addressing for data and additional data portions
Systems, apparatuses, and methods related to addressing for data and additional data portions are described herein. In an example method, addressing for data and additional data portions can include accessing data written to a memory device in response to receipt of a first command configured according to a nondeterministic memory interface protocol. The first command can be a compute express link (CXL) protocol compliant command. The example method can further include converting an address associated with the first command to a second command configured according to a standardized deterministic memory interface protocol. The second command can be a DRAM accessible command. The example method can further include accessing a page of memory cells of the memory device in which the data is written, and in which additional data portions associated with the data are written using the converted address associated with the first command.
1. A method, comprising:
accessing data written to a memory device in response to receipt of a first command configured according to a nondeterministic memory interface protocol,
wherein the first command is a compute express link (CXL) protocol compliant command;
converting an address associated with the first command to a second command configured according to a standardized deterministic memory interface protocol, wherein the second command is a DRAM accessible command and wherein converting the address associated with the first command comprises:
determining a sector in the memory device that includes a page of memory cells including the data;
assigning a sector value to identify the sector, wherein the sector comprises a number of most significant address bits, wherein the significance of the address bits is a physical capacity for which numbers and types of bits are to be used for which address correlation, and wherein the most significant address bits have the largest physical capacity; and
assigning remaining address bits of the number of address bits to different address bit modes, wherein the different address bit modes comprise less significant address bits than the sector;
accessing the page of memory cells of the memory device in which the data is written, and in which additional data portions associated with the data are written using the second command that comprises the converted address associated with the first command.
2. The method of claim 1 , wherein:
the data accessed is 64 bytes in size; and
the additional data portions are cyclic redundancy check (CRC) data portions or error correction code (ECC) portions.
3. The method of claim 2 , wherein:
the additional data portions associated with the data are the CRC portions and are within a range of 24 bits to 28 bits in size; and
metadata associated with the CRC data portions are within a range of 4 bits to 8 bits.
4. The method of claim 3 , wherein the metadata comprises a host poison bit and a memory device poison bit.
5. The method of claim 1 , wherein the page comprises a plurality of portions of data, each of the plurality of portions of data are 64 bytes in size.
6. The method of claim 5 , wherein the plurality of portions of data are consecutively stored in the page and a plurality of portions of additional data associated with each of the plurality of portions of data are consecutively stored in the page.
7. An apparatus, comprising:
a memory controller configured to receive a command associated with a plurality of memory cells in a memory device; and
a processing device coupled to the plurality of memory cells, the processing device to:
receive signaling indicative of accessing data in a page of memory cells of a memory device according to a compute express link (CXL) protocol;
convert an address associated with the signaling to a DRAM accessible address, wherein the conversion comprises determining a sector that the page of memory cells is within, wherein converting the address associated with the first command comprises the processing device to:
determine a sector in the memory device that includes the page including the data;
assign a sector value to identify the sector, wherein the sector comprises a number of most significant address bits, wherein the significance of the address bits is a physical capacity for which numbers and types of bits are to be used for which address correlation, and wherein the most significant address bits have the largest physical capacity;
assign remaining address bits of the number of address bits to different address bit modes, wherein the different address bit modes comprise less significant address bits than the sector; and
access the page associated with the data in the sector of the memory device, wherein the data and cyclic redundancy check (CRC) data associated with the data are in the page.
8. The apparatus of claim 7 , wherein the portion of data is 64 bytes in size.
9. The apparatus of claim 7 , wherein the page associated with the portion of data is 2048 bytes in size.
10. The apparatus of claim 7 , wherein the sector in the memory device comprises 512 entries and an entry is 64 bytes of data.
11. The apparatus of claim 10 , wherein each of the 512 entries comprises at least 3 bytes of CRC data.
12. The apparatus of claim 7 , wherein the memory device is a Compute Express Link (CXL) compliant memory device.
13. The apparatus of claim 7 , further comprising a ferroelectric field-effect transistor (FeFET) memory device, a dynamic random-access memory (DRAM), ferroelectric random-access memory (FeRAM), or a resistive random-access memory (ReRAM) device, or any combination thereof.
14. A system, comprising:
a host to send a command configured according to a nondeterministic memory interface protocol,
wherein the first command is a compute express link (CXL) protocol compliant command;
a memory device coupled to the host, the memory device comprising:
a memory array comprising a plurality of memory cells; and
a memory controller coupled to the memory array, the memory controller to:
receive the command, wherein the command is associated with a portion of data that is 64 bytes in size;
determine a location within a page of memory and within a sector in the memory array the portion of data is in, wherein:
a sector comprises a plurality of entries of data where each of the plurality of entries comprise data and corresponding cyclic redundancy check (CRC) data:
the sector is assigned a sector value to identify the sector, when the sector comprises a number of most significant address bits, wherein the significance of the address bits is a physical capacity for which numbers and types of bits are to be used for which address correlation, and wherein the most significant address bits have the largest physical capacity;
remaining address bits of the number of address bits are assigned to different address bit modes, wherein the different address bit modes comprise less significant address bits than the sector; and
the location within the page of memory is based on a sector off-set; and
access the page of memory associated with the portion of data in the sector of the memory device.
15. The system of claim 14 , wherein the sector spans at least two rows of memory cells within the memory array.
16. The system of claim 15 , wherein an additional sector begins at an off-set from a beginning of a row of memory cells that the sector terminates in.
17. The system of claim 14 , wherein the memory controller is to receive address bits associated with the portion of data, wherein a first portion of the address bits indicates a particular sector, a particular channel, and a particular offset associated with the location of the portion of data.
18. The system of claim 14 , wherein the memory controller is to determine which channel of a plurality of channels to locate the portion of data, wherein the memory device comprises fifteen (15) channels and each page of memory in the memory array spans one of the fifteen (15) channels.