Systems for coupling decoders to quantum registers
A quantum computing device comprises at least one quantum register including l logical qubits, where l is a positive integer. The quantum computing device further includes a set of d decoder blocks coupled to the at least one quantum register, where d<2*l. In this way, the decoder blocks may share decoding requests generated by the logical qubits.
1. A quantum computing device, comprising:
at least one quantum register including l logical qubits, where l is a positive integer, and where each of the l logical qubits generates syndromes including at least X syndromes and Z syndromes; and
a set of d decoder blocks coupled to the at least one quantum register, where d<2*l, such that fewer than 2 decoder blocks are used to process each syndrome generated by the l logical qubits and to output error estimations for data qubits of the l logical qubits; and wherein each decoder block comprises g Graph Generator (Gr-Gen) modules, where 0<g<1.
2. The quantum computing device of claim 1 , wherein each decoder block is configured to receive decoding requests from a set of n logical qubits, wherein n>1.
3. The quantum computing device of claim 1 , wherein each decoder block further comprises α*l Depth First Search (DFS) engines, where 0<α<1.
4. The quantum computing device of claim 3 , wherein two or more Gr-Gen modules are coupled to each DFS engine via one of a first set of multiplexers.
5. The quantum computing device of claim 4 , wherein each decoder block further comprises β*l Correction (Corr) engines, where 0<β<1.
6. The quantum computing device of claim 5 , wherein two or more DFS engines are coupled to each Corr engine via one of a second set of multiplexers.
7. The quantum computing device of claim 5 , wherein memory requests generated by each Corr engine are routed to memory locations via one or more demultiplexers.
8. The quantum computing device of claim 5 , wherein return signals are routed through each multiplexer of the first and second sets of multiplexers based on round-robin arbitration.
9. A method for a quantum computing device, comprising:
generating syndromes from at least one quantum register including l logical qubits, where l is a positive integer, and where each of the generated syndromes includes at least X syndromes and Z syndromes; and
routing the generated syndromes to a set of d decoder blocks coupled to the at least one quantum register, wherein each decoder block comprises kr Graph Generator (Gr-Gen) modules, where 0<g≤1, and where d<2*l, such that fewer than 2 decoder blocks are used to process each generated syndrome and to output error estimations for data qubits of the l logical qubits.
10. The method of claim 9 , wherein each decoder block is configured to receive decoding requests from a set of n logical qubits, wherein n>1.
11. The method of claim 9 , wherein each Gr-Gen module is configured to generate spanning tree memory (STM) data based on the received syndromes.
12. The method of claim 11 , wherein each decoder block further comprises α*l Depth First Search (DFS) engines, where 0<α<1.
13. The method of claim 11 , further comprising:
at each DFS engine, accessing, via one of a first set of multiplexers, STM data generated by two or more Gr-Gen modules; and
generating edge stacks based on the STM data.
14. The method of claim 13 , wherein each decoder block further comprises β*l Correction (Con) engines, where 0<β<1.
15. The method of claim 14 , further comprising
at each Con engine, accessing, via one of a second set of multiplexers, edge stacks generated by two or more DFS engines; and
generating memory requests based on the accessed edge stacks.
16. The method of claim 15 , further comprising:
routing memory requests generated by each Con engine to memory locations via one or more demultiplexers.
17. The method of claim 15 , further comprising:
routing return signals through each multiplexer of the first and second sets of multiplexers based on round-robin architecture.
18. A quantum computing device, comprising:
at least one quantum register including l logical qubits, where l is a positive integer; and
a set of d decoder blocks coupled to the at least one quantum register, wherein d<2*l, and each decoder block comprises:
g Graph Generator (Gr-Gen) modules, where 0<g≤1, each Gr-Gen module configured to generate spanning tree memory (S TM) data based on syndromes received from two or more of the l logical qubits;
α*l Depth First Search (DFS) engines, where 0<α<1, and each DFS engine is configured to:
access, via one of a first set of multiplexers, STM data generated by two or more Gr-Gen generators; and
generate edge stacks based on the STM data; and
β*l Correction (Con) engines, where 0<β<1, and each Con engine is configured to:
access, via one of a second set of multiplexers, edge stacks generated by two or more DFS engines;
generate memory requests based on the accessed edge stacks; and
route the generated memory requests to memory locations via one or more demultiplexers.
19. The quantum computing device of claim 18 , further comprising:
a compression engine coupled to each logical qubit, the compression engine configured to compress syndrome data; and
a decompression engine coupled to each compression engine, each decompression engine configured to:
receive compressed syndrome data;
decompress the received compressed syndrome data; and
route the decompressed syndrome data to a decoder of the set of d decoder blocks.