Dual read port latch array bitcell
An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.
1. A circuit comprising:
an array of memory bit cells for storing data, wherein a given memory bit cell of the array comprises:
a data storage circuit;
a first asymmetrical read access circuit configured to receive a complementary value of the data stored by the data storage circuit; and
a second asymmetrical read access circuit configured to receive the complementary value of the data stored by the data storage circuit, wherein the second asymmetrical read access circuit comprises more transistors of an n-type or a p-type than the first asymmetrical read access circuit; and
wherein in response to receiving an indication of a first read operation, the first asymmetrical read access circuit is configured to:
access the complementary value of the data stored by the data storage circuit; and
convey data stored by the data storage circuit to a first read bit line.
2. The circuit as recited in claim 1 , wherein the circuit further comprises first pre-charge circuitry configured to pre-charge the first read bit line to a ground reference level.
3. The circuit as recited in claim 1 , wherein the second asymmetrical read access circuit comprises only n-type transistors.
4. The circuit as recited in claim 3 , wherein in response to receiving, concurrently with the first read operation, a second read operation targeting a same row of the array targeted by the first read operation, the given memory bit cell, via the second asymmetrical read access circuit, is configured to:
access the complementary value of the data stored by the data storage circuit concurrently with the first asymmetrical read access circuit; and
convey the data stored by the data storage circuit to a second read bit line using the more transistors of an n-type or a p-type than the first asymmetrical read access circuit.
5. The circuit as recited in claim 1 , wherein the data storage circuit is coupled to a write bit line via a pass gate comprising a n-type transistor and a p-type transistor.
6. The circuit as recited in claim 1 , wherein the first asymmetrical read access circuit comprises only p-type transistors that include:
a first p-type transistor configured to receive, on its gate terminal, the complementary value of the data stored by the data storage circuit; and
a second p-type transistor in series with the first p-type transistor configured to:
receive, on its gate terminal, a read word line as the indication of the first read operation; and
receive, on its drain terminal, the first read bit line.
7. The circuit as recited in claim 5 , wherein a gate of the n-type transistor of the pass gate is coupled to receive a write word line, and a gate of the p-type transistor of the pass gate is coupled to receive a signal with a complementary value of the write word line.
8. The circuit as recited in claim 7 , wherein the signal with the complementary value of the write word line is coupled to a gate of an n-type transistor.
9. A method comprising:
storing data in an array of memory bit cells, wherein a given memory bit cell of the array comprises:
storing data by a data storage circuit;
receiving, by a first asymmetrical read access circuit, a complementary value of the data stored by the data storage circuit; and
receiving, by a second asymmetrical read access circuit, the complementary value of the data stored by the data storage circuit, wherein the second asymmetrical read access circuit comprises more transistors of an n-type or a p-type than the first asymmetrical read access circuit; and
wherein in response to receiving an indication of a first read operation, performing, by the first asymmetrical read access circuit of the given memory bit cell of the array:
disabling a pass gate comprising a n-type transistor and a p-type transistor;
accessing the complementary value of the data stored by the data storage circuit of the given memory bit cell; and
conveying the data stored by the data storage circuit to a first read bit line.
10. The method as recited in claim 9 , further comprising pre-charging, by first pre-charge circuitry, the first read bit line to a ground reference level.
11. The method as recited in claim 9 , further comprising receiving the complementary value of the data stored by the data storage circuit by the second asymmetrical read access circuit comprising only n-type transistors.
12. The method as recited in claim 11 , further comprising pre-charging a second read bit line to a power supply reference level.
13. The method as recited in claim 12 , wherein in response to receiving, concurrently with the first read operation, a second read operation targeting a same row of the array targeted by the first read operation, the method further comprises performing by the second asymmetrical read access circuit:
accessing the complementary value of the data stored by the data storage circuit; and
conveying the data stored by the data storage circuit to the second read bit line using the more transistors of an n-type or a p-type than the first asymmetrical read access circuit.
14. The method as recited in claim 9 , further comprising:
receiving, by a gate terminal of a first p-type transistor of the first asymmetrical read access circuit comprising only p-type transistors, a complementary value of the data stored by the data storage circuit;
receiving, on a gate terminal of a second p-type transistor in series with the first p-type transistor, a read word line as the indication of the first read operation; and
receiving, by a drain terminal of the second p-type transistor, the first read bit line.
15. The method as recited in claim 9 , wherein disabling the pass gate comprising receiving a write word line on a gate of the n-type transistor of the pass gate, and receiving a complementary value of the write word line on a gate of the p-type transistor of the pass gate.