Epitaxy regions extending below STI regions and profiles thereof
View Patent ↗A method includes forming isolation regions extending into a semiconductor substrate, forming a plurality of semiconductor fins protruding higher than top surfaces of the isolation regions, forming a gate stack on the plurality of semiconductor fins, forming a gate spacer on a sidewall of the gate stack, and recessing the plurality of semiconductor fins to form a plurality of recesses on a side of the gate stack. The plurality of recesses extend to a level lower than top surfaces of the isolation regions. Epitaxy processes are performed to grow an epitaxy region, wherein the epitaxy region fills the plurality of recesses.
1. A device comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a semiconductor fin between the isolation regions, wherein the semiconductor fin protrudes higher than top surfaces of the isolation regions;
a gate stack on a top surface and sidewalls of the semiconductor fin; and
an epitaxy source/drain region on a side of the semiconductor fin, wherein the epitaxy source/drain region extends to a level lower than top surfaces of the isolation regions, and wherein the epitaxy source/drain region comprises:
a first semiconductor layer having a first dopant concentration; and
an embedded stressor over and contacting the first semiconductor layer, wherein the embedded stressor has a second dopant concentration higher than the first dopant concentration, and wherein the embedded stressor has an upper portion higher than the top surface of the semiconductor fin, and a lower portion lower than the top surface of the semiconductor fin.
2. The device of claim 1 , wherein the embedded stressor comprises silicon phosphorous, and the device further comprises a capping layer over the embedded stressor, and wherein the capping layer comprises silicon, germanium, and phosphorous.
3. The device of claim 1 further comprising a first fin spacer and a second fin spacer on opposing sides of the semiconductor fin, wherein the first semiconductor layer has an additional top surface, and a lowest point of the additional top surface is level with or lower than top ends of the first fin spacer and the second fin spacer.
4. The device of claim 3 , wherein the lowest point of the additional top surface of the first semiconductor layer is level with the top ends of the first fin spacer and the second fin spacer.
5. The device of claim 3 , wherein the lowest point of the additional top surface is lower than the top ends of the first fin spacer and the second fin spacer.
6. The device of claim 1 further comprising a source/drain silicide region over and contacting the epitaxy source/drain region, wherein the source/drain silicide region has a V-shape in a cross-sectional view of the epitaxy source/drain region.
7. The device of claim 1 , wherein the epitaxy source/drain region has a wavy top surface, and the epitaxy source/drain region is of n-type, and the device further comprises:
additional isolation regions extending into the semiconductor substrate;
an additional semiconductor fin protruding higher than top surfaces of the additional isolation regions;
an additional gate stack on a top surface and sidewalls of the additional semiconductor fin; and
an additional epitaxy source/drain region on a side of the additional semiconductor fin, wherein the additional epitaxy source/drain region extends to an additional level lower than top surfaces of the additional isolation regions, and a top portion of the additional epitaxy source/drain region has a cone shape, and wherein the additional epitaxy source/drain region is of p-type.
8. A device comprising:
a semiconductor fin;
isolation regions on opposing sides of the semiconductor fin, wherein the semiconductor fin protrudes higher than top surfaces of the isolation regions;
a gate stack on the semiconductor fin; and
an epitaxy semiconductor region on a side of the semiconductor fin, wherein the epitaxy semiconductor region extends to a first level lower than top surfaces of the isolation regions, and wherein the epitaxy semiconductor region comprises an embedded stressor, and the embedded stressor comprises:
a V-shaped bottom surface, wherein a top end of the V-shaped bottom surface is at a second level lower than a top surface of the semiconductor fin; and
a V-shaped top surface, wherein a portion of the V-shaped top surface is higher than the top surface of the semiconductor fin.
9. The device of claim 8 further comprising a semiconductor layer underlying the embedded stressor, wherein the semiconductor layer comprises a facet on a (111) surface plane of the semiconductor layer.
10. The device of claim 9 , wherein the facet on the (111) surface plane extends to join a top corner of the semiconductor fin.
11. The device of claim 8 further comprising a first fin spacer and a second fin spacer on opposing sides of a portion of the epitaxy semiconductor region, wherein the embedded stressor has a bottommost point higher than a first top end of the first fin spacer.
12. The device of claim 11 , wherein the bottommost point of the embedded stressor is lower than a second top end of the second fin spacer.
13. The device of claim 8 , wherein the epitaxy semiconductor region further comprises an additional semiconductor region underlying the embedded stressor, and wherein the additional semiconductor region extends to the first level lower than the top surfaces of the isolation regions.
14. The device of claim 8 further comprising:
a top semiconductor layer over the embedded stressor; and
a conductive region comprising a silicide region and a contact plug, wherein the conductive region penetrates through the top semiconductor layer to contact the embedded stressor.
15. A device comprising:
a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a semiconductor fin between the isolation regions, wherein the semiconductor fin protrudes higher than top surfaces of the isolation regions;
a gate stack on a top surface and sidewalls of the semiconductor fin;
a gate spacer contacting the gate stack; and
an epitaxy source/drain region on a side of the semiconductor fin, wherein the epitaxy source/drain region extends to a level lower than top surfaces of the isolation regions, and wherein the epitaxy source/drain region comprises:
a first semiconductor layer having a first dopant concentration; and
an embedded stressor over and contacting the first semiconductor layer, wherein the embedded stressor has a second dopant concentration higher than the first dopant concentration, and wherein the embedded stressor comprises:
an upper portion higher than the top surface of the semiconductor fin to contact a sidewall of the gate spacer; and
a lower portion lower than the top surface of the semiconductor fin.
16. The device of claim 15 , wherein the embedded stressor comprises silicon phosphorous, and the device further comprises a capping layer over the embedded stressor, and wherein the capping layer comprises silicon, germanium, and phosphorous.
17. The device of claim 15 further comprising a first fin spacer and a second fin spacer on opposing sides of the semiconductor fin, wherein the first semiconductor layer has an additional top surface, and a lowest point of the additional top surface is level with or lower than top ends of the first fin spacer and the second fin spacer.
18. The device of claim 17 , wherein the lowest point of the additional top surface of the first semiconductor layer is level with or lower than the top ends of the first fin spacer and the second fin spacer.
19. The device of claim 15 further comprising a source/drain silicide region over and contacting the epitaxy source/drain region, wherein the source/drain silicide region has a V-shape in a cross-sectional view of the epitaxy source/drain region.
20. The device of claim 15 , wherein the epitaxy source/drain region has a wavy top surface, and the epitaxy source/drain region is of n-type, and the device further comprises:
additional isolation regions extending into the semiconductor substrate;
an additional semiconductor fin protruding higher than top surfaces of the additional isolation regions;
an additional gate stack on a top surface and sidewalls of the additional semiconductor fin; and
an additional epitaxy source/drain region on a side of the additional semiconductor fin, wherein the additional epitaxy source/drain region extends to an additional level lower than top surfaces of the additional isolation regions, and a top portion of the additional epitaxy source/drain region has a cone shape, and wherein the additional epitaxy source/drain region is of p-type.