Gate structure and method

1. A device, comprising:

a semiconductor nanostructure over a substrate; and

a gate structure over and laterally surrounding the semiconductor nanostructure, the gate structure including:

a first dielectric layer including a first dielectric material having dopants, wherein a greatest concentration of the dopants decreases as a distance to the semiconductor nanostructure decreases;

a second dielectric layer on the first dielectric layer, and including a second dielectric material substantially free of the dopants; and

a metal layer over the second dielectric layer.

2. The device of claim 1 , wherein the greatest concentration of the dopants decreases as a distance from the metal layer increases.

3. The device of claim 1 , wherein the dopants include at least one of ions of lanthanum, magnesium, yttrium, titanium, aluminum, niobium or boron.

4. The device of claim 1 , wherein the gate structure further comprises:

a work function metal layer between the second dielectric layer and the metal layer; and

a work function barrier layer between the work function metal layer and the second dielectric layer.

5. The device of claim 4 , wherein the work function barrier layer comprises at least one of TiN, WN, MON, or TaN.

6. The device of claim 1 , wherein the gate structure further comprises:

a work function metal layer between the second dielectric layer and the metal layer;

a first interfacial layer between the first dielectric layer and the semiconductor nanostructure; and

a second interfacial layer between the work function metal layer and the second dielectric layer.

7. The device of claim 1 , wherein the device includes a fin-type field-effect transistor (FinFET) device or a gate-all-around device.

8. A device, comprising:

a first gate structure including:

a first dielectric layer comprising a first dielectric material including dopants, wherein a greatest concentration of the dopants decreases as a distance to a semiconductor nanostructure decreases;

a second dielectric layer on the first dielectric layer, and including a second dielectric material substantially free of the dopants; and

a first metal layer over the second dielectric layer; and

a second gate structure including:

a third dielectric layer including a third dielectric material substantially free of the dopants;

a fourth dielectric layer on the third dielectric layer, and including a fourth dielectric material substantially free of the dopants; and

a second metal layer over the fourth dielectric layer.

9. The device of claim 8 , wherein the dopants include at least one of ions of lanthanum, magnesium, yttrium, titanium, aluminum, niobium or boron.

10. The device of claim 8 , further comprising:

a third gate structure including:

a fifth dielectric layer having a fifth dielectric material;

a sixth dielectric layer over the fifth dielectric layer; and

a third metal layer over the sixth dielectric layer;

wherein concentration of dopants in the fifth dielectric material is different than the concentration of dopants in the first dielectric material and the concentration of dopants in the third dielectric material.

11. The device of claim 10 , wherein:

the first gate structure further comprises a first work function metal layer between the second dielectric layer and the first metal layer;

the second gate structure further comprises a second work function metal layer having substantially the same composition as the first work function metal layer, the second work function metal layer being between the fourth dielectric layer and the second metal layer; and

the third gate structure further comprises:

a third work function metal layer having substantially the same composition as the first work function metal layer, the third work function metal layer being between the sixth dielectric layer and the third metal fill layer; and

a work function barrier layer between the third work function metal layer and the sixth dielectric layer.

12. The device of claim 11 , wherein the first work function metal layer includes:

an N-type work function metal layer;

an in-situ capping layer on the N-type work function metal layer; and

an oxygen blocking layer on the in-situ capping layer.

13. The device of claim 11 , wherein the first gate structure further comprises an interfacial layer between the first work function metal layer and the second dielectric layer, the interfacial layer comprising TiSiNO.

14. A method, comprising:

forming a first tuning dielectric layer over a first dielectric layer, wherein the first dielectric layer is over a first semiconductor nanostructure associated with a first gate structure, a second semiconductor nanostructure associated with a second gate structure and a third semiconductor nanostructure associated with a third gate structure;

removing the first tuning dielectric layer over the second semiconductor nanostructure and the third semiconductor nanostructure;

forming a second tuning dielectric layer over the first dielectric layer, wherein the second tuning dielectric layer is over the first, second and third semiconductor nanostructures;

removing the second tuning dielectric layer over the third semiconductor nanostructure;

driving in dopants from the first and second tuning dielectric layers to the first dielectric layer over the first semiconductor nanostructure and from the second tuning dielectric layer to the first dielectric layer over the second semiconductor nanostructure;

removing the first and second tuning dielectric layers over the first dielectric layer;

forming a second dielectric layer over the first dielectric layer; and

forming a metal layer over the second dielectric layer.

15. The method of claim 14 , further comprising:

forming a work function barrier layer over the second dielectric layer before the forming a metal layer; and

forming a work function metal layer over the work function barrier layer before the forming a metal layer.

16. The method of claim 14 , further comprising:

forming a first interfacial layer on the first semiconductor nanostructure and the second semiconductor nanostructure before the forming a first tuning dielectric layer; and

forming a second interfacial layer on the second dielectric layer before the forming a metal layer.

17. The method of claim 16 , wherein the forming a second interfacial layer includes:

forming a high-k capping layer on the second dielectric layer;

forming the second interfacial layer by a thermal anneal performed on the high-k capping layer; and

removing the high-k capping layer by an artificial-intelligence-controlled atomic layer etch process.

18. The method of claim 14 , wherein the forming a second tuning dielectric layer is after the removing a first tuning dielectric layer and before the driving in the dopants.

19. The method of claim 14 , further comprising:

forming a work function metal layer over the second dielectric layer before the forming a metal layer, including:

forming an N-type work function metal layer;

forming an in-situ capping layer on the N-type work function metal layer; and

forming an oxygen blocking layer on the in-situ capping layer.

20. The method of claim 19 , further comprising:

forming a glue layer on the work function metal layer;

wherein the metal layer is formed on the glue layer.