Power pack and power pack circuitry
A multi-level power cell pack switching circuitry having a plurality of first level cell circuits, and additional plurality of cell circuits of consecutively progressing levels, with switching and control configured to facilitate dynamically changing serial and/or parallel connections between cells and cell circuits.
1. A multi-level power cell pack switching circuitry comprising:
a plurality of first level cell circuits for connecting a plurality of power cells, the plurality of first level cell circuits comprising: 1) a first cell circuit, 2) a second cell circuit, 3) a third cell circuit, and 4) a fourth cell circuit, wherein
the first cell circuit comprises:
a first cell having a positive terminal and a negative terminal;
a second cell having a positive terminal and a negative terminal;
a first switch for connecting the positive terminal of the first cell to a first node of the first cell circuit;
a second switch for connecting the positive terminal of the second cell to the first node of the first cell circuit;
a third switch for connecting the negative terminal of the first cell to a second node of the first cell circuit;
a fourth switch for connecting the negative terminal of the second cell to the second node of the first cell circuit; and
a fifth switch for connecting the positive terminal of the first cell to the negative terminal of the second cell,
the second cell circuit comprises:
a third cell having a positive terminal and a negative terminal;
a fourth cell having a positive terminal and a negative terminal;
a sixth switch for connecting the positive terminal of the third cell to a first node of the second cell circuit;
a seventh switch for connecting the positive terminal of the fourth cell to the first node of the second cell circuit;
an eighth switch for connecting the negative terminal of the third cell to a second node of the second cell circuit;
a ninth switch for connecting the negative terminal of the second cell to the second node of the second cell circuit; and
a tenth switch for connecting the positive terminal of the third cell to the negative terminal of the fourth cell,
the third cell circuit comprises:
a fifth cell having a positive terminal and a negative terminal;
a sixth cell having a positive terminal and a negative terminal;
an eleventh switch for connecting the positive terminal of the fifth cell to a first node of the third cell circuit;
a twelfth switch for connecting the positive terminal of the sixth cell to the first node of the third cell circuit;
a thirteenth switch for connecting the negative terminal of the fifth cell to a second node of the third cell circuit;
a fourteenth switch for connecting the negative terminal of the sixth cell to the second node of the third cell circuit; and
a fifteenth switch for connecting the positive terminal of the fifth cell to the negative terminal of the sixth cell,
the fourth cell circuit comprises:
a seventh cell having a positive terminal and a negative terminal;
an eighth cell having a positive terminal and a negative terminal;
a sixteenth switch for connecting the positive terminal of the seventh cell to a first node of the fourth cell circuit;
a seventeenth switch for connecting the positive terminal of the eighth cell to the first node of the fourth cell circuit;
an eighteenth switch for connecting the negative terminal of the seventh cell to a second node of the fourth cell circuit;
a nineteenth switch for connecting the negative terminal of the eighth cell to the second node of the fourth cell circuit; and
a twentieth switch for connecting the positive terminal of the seventh cell to the negative terminal of the eighth cell;
a twenty-first switch for connecting the first node of the first cell circuit to a third node;
a twenty-second switch for connecting the second node of the first cell circuit to a fourth node;
a twenty-third switch for connecting the first node of the second cell circuit to the third node;
a twenty-fourth switch for connecting the second node of the second cell circuit to the fourth node;
a twenty-fifth switch for connecting the first node of the first cell circuit to the second node of the second cell circuit;
a twenty-sixth switch for connecting the first node of the third cell circuit to a fifth node;
a twenty-seventh switch for connecting the second node of the third cell circuit to a sixth node;
a twenty-eighth switch for connecting the first node of the fourth cell circuit to the fifth node;
a twenty-ninth switch for connecting the second node of the fourth cell circuit to the sixth node;
a thirtieth switch for connecting the first node of the third cell circuit to the second node of the fourth cell circuit; and
a thirty-first switch for connecting the third node to the sixth node.
2. The switching circuitry of claim 1 , embodied in an electronic chip.
3. The switching circuitry of claim 1 , further comprising sensors for sensing one or a plurality of performance parameters of the power cells.
4. The switching circuitry of claim 3 , wherein the performance parameters are selected from a group consisting of: current, voltage, temperature, pressure, humidity, impedance, SOC, SOH and recorded history.
5. The switching circuitry of claim 1 , further comprising a controller configured to operate the switches, so as to allow connecting power cells of said plurality of power cells or a plurality of cell circuits of said plurality of cell circuits of consecutively progressing levels, or a first combination thereof, in parallel, in series or in a second combination thereof, and to change any of the first or second combinations, and so as to allow connecting or disconnecting one or a plurality of the power cells, or one or a plurality of the cell circuits.
6. The switching circuitry of claim 5 , further comprising sensors for sensing one or a plurality of performance parameters of the power cells, and wherein the controller is configured to operate the switches according to a switching scheme based on the sensed one or a plurality of performance parameters.
7. The switching circuitry of claim 6 , wherein the performance parameters are selected from a group consisting of: current, voltage, temperature, pressure, impedance, humidity, SOC, SOH and recorded history.
8. A power pack comprising:
a plurality of power cells, each of the power cells having a positive terminal and a negative terminal; and
a multi-level power cell pack switching circuitry comprising:
a plurality of first level cell circuits for connecting the plurality of power cells, wherein, the plurality of first level cell circuits comprises: 1) a first cell circuit, 2) a second cell circuit, 3) a third cell circuit, and 4) a fourth cell circuit, wherein
the first cell circuit comprises:
a first cell having a positive terminal and a negative terminal;
a second cell having a positive terminal and a negative terminal;
a first switch for connecting the positive terminal of the first cell to a first node of the first cell circuit;
a second switch for connecting the positive terminal of the second cell to the first node of the first cell circuit;
a third switch for connecting the negative terminal of the first cell to a second node of the first cell circuit;
a fourth switch for connecting the negative terminal of the second cell to the second node of the first cell circuit; and
a fifth switch for connecting the positive terminal of the first cell to the negative terminal of the second cell,
the second cell circuit comprises:
a third cell having a positive terminal and a negative terminal;
a fourth cell having a positive terminal and a negative terminal;
a sixth switch for connecting the positive terminal of the third cell to a first node of the second cell circuit;
a seventh switch for connecting the positive terminal of the fourth cell to the first node of the second cell circuit;
an eighth switch for connecting the negative terminal of the third cell to a second node of the second cell circuit;
a ninth switch for connecting the negative terminal of the second cell to the second node of the second cell circuit; and
a tenth switch for connecting the positive terminal of the third cell to the negative terminal of the fourth cell, the third cell circuit comprises:
a fifth cell having a positive terminal and a negative terminal;
a sixth cell having a positive terminal and a negative terminal;
an eleventh switch for connecting the positive terminal of the fifth cell to a first node of the third cell circuit;
a twelfth switch for connecting the positive terminal of the sixth cell to the first node of the third cell circuit;
a thirteenth switch for connecting the negative terminal of the fifth cell to a second node of the third cell circuit;
a fourteenth switch for connecting the negative terminal of the sixth cell to the second node of the third cell circuit; and
a fifteenth switch for connecting the positive terminal of the fifth cell to the negative terminal of the sixth cell,
the fourth cell circuit comprises:
a seventh cell having a positive terminal and a negative terminal;
an eighth cell having a positive terminal and a negative terminal;
a sixteenth switch for connecting the positive terminal of the seventh cell to a first node of the fourth cell circuit;
a seventeenth switch for connecting the positive terminal of the eighth cell to the first node of the fourth cell circuit;
an eighteenth switch for connecting the negative terminal of the seventh cell to a second node of the fourth cell circuit;
a nineteenth switch for connecting the negative terminal of the eighth cell to the second node of the fourth cell circuit; and
a twentieth switch for connecting the positive terminal of the seventh cell to the negative terminal of the eighth cell;
a twenty-first switch for connecting the first node of the first cell circuit to a third node;
a twenty-second switch for connecting the second node of the first cell circuit to a fourth node;
a twenty-third switch for connecting the first node of the second cell circuit to the third node;
a twenty-fourth switch for connecting the second node of the second cell circuit to the fourth node;
a twenty-fifth switch for connecting the first node of the first cell circuit to the second node of the second cell circuit;
a twenty-sixth switch for connecting the first node of the third cell circuit to a fifth node;
a twenty-seventh switch for connecting the second node of the third cell circuit to a sixth node;
a twenty-eighth switch for connecting the first node of the fourth cell circuit to the fifth node;
a twenty-ninth switch for connecting the second node of the fourth cell circuit to the sixth node;
a thirtieth switch for connecting the first node of the third cell circuit to the second node of the fourth cell circuit; and
a thirty-first switch for connecting the third node to the sixth node.
9. The power pack of claim 8 , wherein the switching circuitry is embodied in an electronic chip.
10. The power pack of claim 8 , further comprising sensors for sensing one or a plurality of performance parameters of the power cells.
11. The power pack of claim 10 , wherein the performance parameters are selected from a group consisting of: current, voltage, temperature, pressure, impedance, SOC, SOH and saved history.
12. The power pack of claim 8 , further comprising a controller configured to operate the switches, so as to allow connecting power cells of said plurality of power cells or a plurality of cell circuits of said plurality of cell circuits of consecutively progressing levels, or a first combination thereof, in parallel, in series or in a second combination thereof, and to change any of the first or second combinations, and so as to allow connecting or disconnecting one or a plurality of the power cells, or one or a plurality of the cell circuits.
13. The power pack of claim 12 , further comprising sensors for sensing one or a plurality of performance parameters of the power cells, and wherein the controller is configured to operate the switches according to a switching scheme based on the sensed one or a plurality of performance parameters.
14. The power pack of claim 13 , wherein the performance parameters are selected from a group consisting of: current, voltage, temperature, pressure, impedance, SOC, SOH and saved history.
15. The power pack of claim 8 , wherein the power cells are selected from the group consisting of: battery cells, fuel cells, capacitors and photovoltaic cells.